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參數(shù)資料
| 型號： | IDT72T54242L5BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| 中文描述： | 32K X 20 OTHER FIFO, 3.6 ns, PBGA324 |
| 封裝： | 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324 |
| 文件頁數(shù)： | 17/56頁 |
| 文件大?。?/td> | 555K |
| 代理商： | IDT72T54242L5BB |
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17
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
FUNCTIONAL DESCRIPTION
MASTER RESET & DEVICE CONFIGURATION
During Master Reset the device configuration and settings are determned,
this includes the following:
1. Quad or Dual mode
2. IDT Standard or First Word Fall Through (FWFT) flag timng mode
3. Single or Double Data Rates on both the Write and Read ports
4. Programmable flag mode, synchronous or asynchronous timng
5. Write and Read Port Bus Widths, x10 or x20 (in Dual mode only)
6. Default Offsets for the programmable flags, 7, 63, 127, or 1023
7. LVTTL or HSTL I/O selection
The state of the configuration inputs during master reset will determne which
of the above modes are selected.
A master reset comprises of pulsing the
MRS
input pin fromhigh to low for a period of time (t
RS
) with the configuration inputs
held in their respective states. Table 1 summarizes the configuration modes
available during master reset. They are described as follows:
Quad or Dual mode.
This mode is selected using the MD input.
If during
master reset, MD is HIGH then Quad mode is selected, if MD is LOW then Dual
mode is selected.
In Quad mode four independent FIFOs are available, while
in Dual mode two independent FIFOs are available.
IDT Standard or FWFT mode
. The two available flag timng modes are
selected using the FWFT/SI input. If FWFT/SI is LOW during master reset then
IDT Standard mode is selected, if it is high then FWFT mode is selected.
The
timng modes are described later in this section.
Single Data Rate (SDR) or Double Data Rate (DDR).
The input/output
data rates are port selectable. This is a versatile feature that allows the user to
select either SDR or DDR on the write ports and/or read ports of all FIFOs using
the WDDR and RDDR inputs. If WDDR is LOW during master reset then the write
ports of all FIFOs will function in SDR mode; if it is high then the write ports will
be DDR mode.
If RDDR is LOW during master reset then the read ports of all
FIFOs will function in SDR mode; if it is high then the read port will be DDR mode.
This feature is described in the Signal Descriptions section.
Programmable Almost Empty/Full Flags
. These flags can operate in
either synchronous or asynchronous timng mode. If the programmable flag
input, PFMis HIGH during master reset then all programmable flags will operate
in a synchronous manner, meaning the
PAE
flags are double buffered and
updated based on the rising edge of its respective read clocks. The
PAF
flags
are also double buffered and updated based on the rising edge of its respective
write clocks. If it is LOW then all programmable flags will operate in an
asynchronous manner, meaning the
PAE
and
PAF
flags are not double buffered
and will update through the internal counter after a nomnal delay.
This feature
is described in the Signal Descriptions section.
Selectable Bus Width
.
In Dual mode, the bus width can be selected on
the read and write ports using the IW and OW inputs.
If IW is LOW then the write
ports will be 10 bits wide, if IW is HIGH then the write ports will be 20 bits wide.
If OW is LOW then the read ports will be 10 bits wide, if OW is HIGH then the read
ports will be 20 bits wide.
Note in Quad mode the inputs and outputs are always
10 bits wide regardless of the state of these pins.
This feature is described in the
Signal Descriptions section.
Programmable Flag Offset Values.
These offset values can be user
programmed or they can be set to one of four default values during a master
reset. For default programmng, the state of the FSEL[1:0] inputs during master
reset will determne the value. Table 2, Default Programmable offsets lists the
four offset values and how to select them For programmng the offset values to
a specific number, use the serial programmng signals (SCLK,
SWEN
,
SREN
,
FWFT/SI) to load the value into the offset register. You may also use the JTAG
port on this device to load the offset value. Keep in mnd that you must disable
the serial programmng signals if you plan to use the JTAG port for loading the
offset values. To disable the serial programmng signals, tie SCLK,
SWEN
,
SREN
, and FWFT/SI to V
CC
.
A thorough explanation of the serial and JTAG
programmng of the flag offset values is provided in the "Serial Write and Reading
of Offset Registers” section.
I/O Level Selection.
The I/Os can be selected for either 2.5V LVTTL levels
or 1.5V HSTL / 1.8V eHSTL levels. The state of the IOSEL input will determne
which I/O level will be selected. If IOSEL is HIGH then the applicable I/Os will
be 1.5V HSTL or 1.8V eHSTL, depending on the voltage level applied to V
DDQ
and V
REF
. For HSTL, VDDQ
and V
REF
= 1.5V and for eHSTL VDDQ
and V
REF
= 1.8V. If IOSEL is LOW then the applicable I/Os will be 2.5V LVTTL. As noted
in the Pin Description section, IOSEL is a CMOS input and must be tied to either
V
CC
or GND for proper operation.
TABLE 1 — DEVICE CONFIGURATION
PINS
VALUES
MD
0
Dual mode
1
Quad mode
FWFT/SI
0
IDT Standard mode
1
FWFT mode
WDDR
0
Single Data Rate write port
1
Double Data Rate write port
RDDR
0
Single Data Rate read port
1
Double Data Rate read port
PFM
0
Asynchronous operation of
PAE
and
PAF
outputs
1
Synchronous operation of
PAE
and
PAF
outputs
IW
0
Write port is 10 bits wide
1
Write port is 20 bits wide in dual mode, 10 bits wider
in Dual mode
OW
0
Read port is 10 bits wide
1
Read port is 20 bits wide in dual mode, 10 bits wider
in Dual mode
FSEL[1:0]
00
Programmable flag registers offset value = 7
01
Programmable flag registers offset value = 63
10
Programmable flag registers offset value = 127
11
Programmable flag registers offset value = 1023
IOSEL
0
All applicable I/Os (except CMOS) are LVTTL
1
All applicable I/Os (except CMOS) are HSTL/eHSTL
CONFIGURATION
IDT72T54242
IDT72T54252
IDT72T54262
FSEL1
0
0
1
1
FSEL0
0
1
0
1
Offsets n,m
7
63
127
1023
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. In default programmng, the offset value selected applies to all internal FIFOs.
2. To programdifferent offset values for each FIFO, serial programmng must be used.
3. n is the offset value for
PAE
, mis the offset value for
PAF
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T54242L5BBI | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54252 | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54252L5BB | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54252L5BBI | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54262 | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T54242L6-7BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54242L6-7BBI | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54252L5BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54252L6-7BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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