參數(shù)資料
型號： IDT72T54242L5BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
中文描述： 32K X 20 OTHER FIFO, 3.6 ns, PBGA324
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
文件頁數(shù)： 3/56頁
文件大?。?/td> 555K
代理商： IDT72T54242L5BB
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
Table of Contents
Features .........................................................................................................................................................................................................................1
Description......................................................................................................................................................................................................................4
Pin Configuration.............................................................................................................................................................................................................6
Pin Descriptions...............................................................................................................................................................................................................7
Device Characteristics ................................................................................................................................................................................................... 11
DC Electrical Characteristics ..........................................................................................................................................................................................12
AC Electrical Characteristics...........................................................................................................................................................................................14
AC Test Conditions........................................................................................................................................................................................................15
Functional Description...................................................................................................................................................................................................17
Signal Descriptions........................................................................................................................................................................................................23
JTAG Timng Specifications ............................................................................................................................................................................................29
List of Tables
Table 1 —Device Configuration....................................................................................................................................................................................17
Table 2 —Default Programmable Flag Offsets................................................................................................................................................................17
Table 3 — Status Flags for IDT Standard mode .............................................................................................................................................................20
Table 4 —Status Flags for FWFT mode ........................................................................................................................................................................20
Table 5 —I/O Voltage Level Associations.......................................................................................................................................................................21
Table 6 — T
SKEW
Measurement ...................................................................................................................................................................................27
List of Figures
Figure 1. Quad/Dual Block Diagram................................................................................................................................................................................5
Figure 2a. AC Test Load................................................................................................................................................................................................15
Figure 2b. Lumped Capacitive Load, Typical Derating ...................................................................................................................................................15
Figure 3. Programmable Flag Offset Programmng Methods...........................................................................................................................................18
Figure 4. Offset Registers Serial Bit Sequence................................................................................................................................................................19
Figure 5. Bus-Matching in Dual mode............................................................................................................................................................................22
Figure 6. Echo Read Clock and Data Output Relationship..............................................................................................................................................27
Figure 7. Standard JTAG Timng ...................................................................................................................................................................................28
Figure 8. JTAG Architecture...........................................................................................................................................................................................29
Figure 9. TAP Controller State Diagram.........................................................................................................................................................................30
Figure 10. Master Reset Timng.....................................................................................................................................................................................33
Figure 11. Partial Reset Timng......................................................................................................................................................................................34
Figure 12. Write Cycle and Full Flag Timng (Quad mode, IDT Standard mode, SDR to SDR) .......................................................................................35
Figure 13. Write Cycle and Full Flag Timng (Quad mode, IDT Standard mode, DDR to DDR).......................................................................................36
Figure 14. Write Cycle and Full Flag Timng (Dual mode, IDT Standard mode, DDR to SDR, x10 In to x20 Out)............................................................37
Figure 15. Write Cycle and Full Flag (Dual mode, IDT Standard mode, SDR to DDR, x20 In to x10 Out).......................................................................38
Figure 16. Write Cycle and Output Ready Timng (Quad mode, FWFT mode, SDR to SDR) ..........................................................................................39
Figure 17. Write Cycle and Output Ready Timng (Quad mode, FWFT mode, DDR to DDR)..........................................................................................40
Figure 18. Read Cycle, Output Enable and Empty Flag Timng (Quad mode, IDT Standard mode, SDR to SDR)...........................................................41
Figure 19. Read Cycle, Output Enable and Empty Flag Timng (Quad mode, IDT Standard mode, DDR to DDR) ..........................................................42
Figure 20. Read Cycle and Empty Flag Timng (Dual mode, IDT Standard mode, DDR to SDR, x20 In to x10 Out).......................................................43
Figure 21. Read Cycle and Empty Flag Timng (Dual mode, IDT Standard mode, SDR to DDR, x10 In to x20 Out).......................................................44
Figure 22. Read Timng and Output Ready Flag (Quad mode, FWFT mode, SDR to SDR) ...........................................................................................45
Figure 23. Read Timng and Output Ready Timng (Quad mode, FWFT mode, DDR to DDR)........................................................................................46
Figure 24. Read Cycle and Read Chip Select (Quad mode, IDT Standard mode, SDR to SDR)....................................................................................47
Figure 25. Read Cycle and Read Chip Select Timng (Quad mode, FWFT mode, SDR to SDR)....................................................................................48
Figure 26. Echo Read Clock and Read Enable Operation (Quad mode, IDT Standard mode, DDR to DDR) .................................................................49
Figure 27. Echo RCLK and Echo Read Enable Operation (Quad mode, FWFT mode, SDR to SDR).............................................................................50
Figure 28. Echo Read Clock and Read Enable Operation (Quad mode, IDT Standard mode, SDR to SDR)..................................................................51
Figure 29. Loading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................52
Figure 30. Reading of Programmable Flag Registers (IDT Standard and FWFT modes)................................................................................................52
Figure 32. Synchronous Programmable Almost-Empty Flag Timng (Quad mode, IDT Standard and FWFT mode, SDR to SDR)...................................53
Figure 31. Synchronous Programmable Almost-Full Flag Timng (Quad mode, IDT Standard and FWFT mode, SDR to SDR).......................................53
Figure 33. Asynchronous Programmable Almost-Full Flag Timng (Quad mode, IDT Standard and FWFT mode, SDR to SDR)......................................54
Figure 34. Asynchronous Programmable Almost-Empty Flag Timng (Quad mode, IDT Standard and FWFT mode, SDR to SDR)..................................54
Figure 35. Power Down Operation................................................................................................................................................................................55
相關PDF資料
PDF描述
IDT72T54242L5BBI 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54252 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54252L5BB 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54252L5BBI 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54262 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
相關代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72T54242L6-7BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54242L6-7BBI 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54252L5BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54252L6-7BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54252L6-7BBI 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應商設備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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