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| 型號： | IDT72T54242L5BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| 中文描述： | 32K X 20 OTHER FIFO, 3.6 ns, PBGA324 |
| 封裝： | 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324 |
| 文件頁數(shù)： | 4/56頁 |
| 文件大小： | 555K |
| 代理商： | IDT72T54242L5BB |
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
DESCRIPTION
The IDT72T54242/72T54252/72T54262 Quad/Dual TeraSync FIFO
devices are ideal for many applications where data streamconvergence and
parallel buffering of multiple data paths are required. These applications may
include communication systems such as data bandwidth aggregation, data
acquisition systems and medical equipment, etc. The Quad/Dual FIFO allows
the user to select either two or four individual internal FIFOs for operation. Each
internal FIFO has its own discrete read and write clock, independent read and
write enables, and separate status flags. The density of each FIFO is fixed.
If Quad mode is selected, there will be a total of eight clock domains, four read
and four write clocks. Data can be written into any of the four write ports totally
independent of any other port, and can be read out of any of the four read ports
corresponding to their respective write port. Each port has its own control
enables and status flags and is 10 bits wide. The device functions as four
separate 10-bit wide FIFOs.
If Dual mode is selected, there will be a total of four clock domains, two read
and two write clocks. Data can be written into any of the two write ports totally
independent of any other port, and can be read out of any of the two read ports
corresponding to their respective write port. Each port has its own control
enables and status flags. All input and output ports have bus-matching
capabilities of x10 or x20 bits wide.
As typical with most IDT FIFOs, two types of data transfer are available, IDT
Standard mode and First Word Fall Through (FWFT) mode. This affects the
device operation and also the flag outputs. The device provides eight flag outputs
per input and output port. A dedicated Serial Clock is used for programmng the
flag offsets. This clock is also used for reading the offset values. The serial read
and write operations are performed via the SCLK, FWFT/SI,
SWEN
,
SREN
,
and SDO pins. The flag offsets can also be programmed using the JTAG port.
If this option is selected, the SCLK,
SWEN
, and
SREN
pins must be disabled.
The Quad/Dual device offers a maximumthroughput of 2Gbps per port, with
selectable SDR or DDR data transfer modes for the inputs and outputs. In SDR
mode, the input clock can operate up to 200MHz. Data will transition/latch on
the rising edge of the clock. In DDR mode, the input clock can operate up to 100
MHz, with data transitioning/latched on both rising and falling edges of the clock.
The advantage of DDR is that it can achieve the same throughput as SDR with
only half the number of bits, assumng the frequency is constant. For example,
a 4Gbps throughput in SDR is 100MHz x 40 bits. In DDR mode, it is 100MHz
x 20 bits, because two bits transition per clock cycle.
All Read ports provide the user with a dedicated Echo Read Enable,
EREN
and Echo Read Clock, ERCLK output. These outputs aid in high speed
applications where synchronization of the input clock and data of receiving
device is critical. Otherwise known as “Source Synchronous Clocking,” the
echo outputs provide tighter synchronization of the data transmtted fromthe
FIFO and the read clock interfacing the FIFO outputs.
A Master Reset input is provided and all setup and configuration pins are
latched with respect to a Master Reset pulse. For example, the mode of
operation, bus-matching, and data rate are selected at Master Reset. A Partial
Reset is provided for each internal FIFO. When a Partial Reset is performed
on a FIFO the read and write pointers of that FIFO are reset to the first memory
location. The flag offset values, timng modes, and initial configurations are
retained.
The Quad/Dual device has the capability of operating its I/O at either 2.5V
LVTTL, 1.5V HSTL or 1.8V eHSTL levels. A Voltage Reference, Vref input
is provided for HSTL and eHSTL interfaces. The type of I/O is selected via the
IOSEL pin. The core supply voltage of the device, V
CC
is always 2.5V, however
the output pins have a separate supply, V
DDQ
which can be 2.5V, 1.8V, or 1.5V.
The inputs of this device are 3.3V tolerant when V
DDQ
is set to 2.5V. The device
also offers significant power savings, most notably achieved by the presence
of a Power Down input,
PD
.
A JTAG test port is provided. The Quad/Dual device has a fully functional
Boundary Scan feature, compliant with IEEE 1149.1 Standard Test Access Port
and Boundary Scan Architecture.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72T54242L5BBI | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54252 | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54252L5BB | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54252L5BBI | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| IDT72T54262 | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72T54242L6-7BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54242L6-7BBI | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54252L5BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54252L6-7BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54252L6-7BBI | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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