參數(shù)資料
型號: IDT72T54242L5BBI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
中文描述: 128K X 10 OTHER FIFO, 3.6 ns, PBGA324
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
文件頁數(shù): 12/56頁
文件大?。?/td> 555K
代理商: IDT72T54242L5BBI
12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
DC ELECTRICAL CHARACTERISTICS
(Industrial: V
CC
= 2.5V ± 0.125V, T
A
= -40
°
C to +85
°
C)
Symbol
I
LI
I
LO
Parameter
Min.
–10
–10
Max.
+10
+10
Unit
μ
A
μ
A
mA
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Input Leakage Current
Output Leakage Current
I
CC3
(2,3)
V
OH
(1)
JTAG Input Leakage Current
Output Logic “1” Voltage,
-16
0.4
0.4
0.4
250
(7)
350
(7)
350
(7)
180
(7)
295
(7)
295
(7)
50
40
40
35
20
20
110
(7)
240
(7)
240
(7)
100
(7)
185
(7)
185
(7)
40
35
35
30
15
15
15
(7)
30
(7)
30
(7)
15
(7)
30
(7)
30
(7)
0.5
0.5
0.5
0.2
0.2
0.2
I
OH
= –8 mA @LVTTL
I
OH
= –8 mA @eHSTL
I
OH
= –8 mA @HSTL
I
OL
= 8 mA @LVTTL
I
OL
= 8 mA @eHSTL
I
OL
= 8 mA @HSTL
-- LVTTL
-- eHSTL
-- HSTL
-- LVTTL
-- eHSTL
-- HSTL
-- LVTTL
-- eHSTL
-- HSTL
-- LVTTL
-- eHSTL
-- HSTL
-- LVTTL
-- eHSTL
-- HSTL
-- LVTTL
-- eHSTL
-- HSTL
-- LVTTL
-- eHSTL
-- HSTL
-- LVTTL
-- eHSTL
-- HSTL
-- LVTTL
-- eHSTL
-- HSTL
-- LVTTL
-- eHSTL
-- HSTL
-- LVTTL
-- eHSTL
-- HSTL
-- LVTTL
-- eHSTL
-- HSTL
V
DDQ
-0.4
V
DDQ
-0.4
V
DDQ
-0.4
V
OL
Output Logic “0” Voltage,
I
CC1
(2,3,4)
Active V
CC
Current (Quad mode)
(See Note 7 for test conditions)
I
CC2
(2,3,4)
Active V
CC
Current (Dual mode)
(See Note 8 for test conditions)
I
DDQ1
(2,3,5)
Active V
DDQ
Current (Quad mode)
(See Note 7 for test conditions)
I
DDQ2
(2,3,5)
Active V
DDQ
Current (Dual mode)
(See Note 8 for test conditions)
I
SB1
(2,3,4)
Standby V
CC
Current (Quad mode)
(See Note 9 for test conditions)
I
SB2
(2,3,4)
Standby V
CC
Current (Dual mode)
(See Note 10 for test conditions)
I
SB3
(2,3,5)
Standby V
DDQ
Current (Quad mode)
(See Note 9 for test conditions)
I
SB4
(2,3,5)
Standby V
DDQ
Current (Dual mode)
(See Note 10 for test conditions)
I
PD1
(3,4)
Power Down V
CC
Current (Quad mode)
(See Note 11 for test conditions)
I
PD2
(3,4)
Power Down V
CC
Current (Dual mode)
(See Note 12 for test conditions)
I
PD3
(3,5)
Power Down V
DDQ
Current (Quad mode)
(See Note 11 for test conditions)
I
PD4
(3,5)
Power Down V
DDQ
Current (Dual mode)
(See Note 12 for test conditions)
NOTES:
1. Outputs are not 3.3V tolerant.
2. All WCLKs and RCLKs toggling at 20MHz. Data inputs toggling at 10MHz.
3. V
CC
= 2.5V,
OE
0-3 = HIGH.
4. Typical I
CC1
calculation
:
for LVTTL I/O: I
CC1
(Quad mode) =
11.25 x
fs
I
CC1
(Dual mode) =
7.74 x
fs
for HSTL I/O: I
CC1
(Quad mode) =
158 + (11.25 x
fs
)
I
CC1
(Dual mode) =
115 + (7.74 x
fs
)
where
fs
= WCLK = RCLK frequency (in MHz)
NOTES CONTINUED ON PAGE 13.
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PDF描述
IDT72T54252 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
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