參數(shù)資料
型號(hào)： IDT72T54242L5BBI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： DRAM
英文描述： 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
中文描述： 128K X 10 OTHER FIFO, 3.6 ns, PBGA324
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
文件頁(yè)數(shù)： 9/56頁(yè)
文件大?。?/td> 555K
代理商： IDT72T54242L5BBI
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
TCK
(3)
JTAG Clock
HSTL-LVTTL Clock input for JTAG function. One of four termnals required by IEEE Standard 1149.1-1990. Test
INPUT
operations of the device are synchronous to TCK. Data fromTMS and TDI are sampled on the
rising edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used
this signal needs to be tied to GND.
HSTL-LVTTL One of four termnals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
INPUT
operation, test data serially loaded via the TDI on the rising edge of TCK to either the Instruction
Register, ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left
unconnected.
HSTL-LVTTL One of four termnals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan
OUTPUT
operation, test data serially loaded output via the TDO on the falling edge of TCK fromeither the
Instruction Register, ID Register and Bypass Register. This output is high impedance except
when shifting, while in SHIFT-DR and SHIFT-IR controller states.
HSTL-LVTTL TMS is a serial input pin. One of four termnals required by IEEE Standard 1149.1-1990. TMS directs
INPUT
the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left
unconnected.
HSTL-LVTTL
TRST
is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not
INPUT
automatically reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH
for five TCK cycles. If the TAP controller is not properly reset then the FIFO outputs will always be
in high-impedance. If the JTAG function is used but the user does not want to use
TRST
, then
TRST
can be tied with
MRS
to ensure proper FIFO operation. If the JTAG function is not used then this signal
needs to be tied to GND. An internal pull-up resistor forces
TRST
HIGH if left unconnected.
HSTL-LVTTL These are the clock inputs corresponding to each of the four FIFOs on the write port. If Dual mode
INPUT
is selected then WCLK1 and WCLK3 are not used and should be tied to GND. In SDR mode data
will be written on the rising edge of WCLK when
WEN
and
WCS
are LOW at the rising edge of WCLK.
In DDR mode data will be written on both rising and falling edge of WCLK when
WEN
and
WCS
are
LOW at the rising edge of WCLK.
HSTL-LVTTL These are the write chip select inputs corresponding to each of the four FIFOs on the write port. This
INPUT
pin can be regarded as a second write enable input, enabling/disabling write operations.
WCS
is
only sampled on the rising edge of WCLK. If Dual mode is selected then
WCS
1 and
WCS
3 are not
used and should be tied to V
CC
.
CMOS
(2)
During master reset, this pin selects the input port to operate in DDR or SDR format. If WDDR is HIGH,
INPUT
then a word is written on the rising and falling edge of the appropriate WCLK0, 1, 2 and 3 input.
If WDDR is LOW, then a word is written only on the rising edge of the appropriate WCLK0, 1, 2 and
3 inputs.
Write Enable 0/1/2/3 HSTL-LVTTL These are the write enable inputs corresponding to each of the four FIFOs on the write port. In SDR,
INPUT
when this signal (and
WCS
) are LOW data on the databus will be written into the FIFO memory on
every rising edge of WCLK. In DDR mode, data will be written on both rising and falling edges of
WCLK. Note in DDR mode the
WEN
and
WCS
are only sampled on the rising edge of WCLK. New
data will always begin writing fromthe rising edge, not the falling edge of WCLK. If Dual mode is
selected then
WEN
1 and
WEN
3 are not used and should be tied to V
CC
.
+2.5V Supply
Power
These are V
CC
core power supply pins and must all be connected to a +2.5V supply rail.
Output Rail Voltage
Power
This pin should be tied to the desired voltage rail for providing to the output drivers. Nomnally 1.5V
or 1.8V for HSTL, 2.5V for LVTTL.
Ground Pin
Ground
These ground pins are for the core device and must be connected to the GND rail.
Reference voltage
Power
This is a Voltage Reference input and must be connected to a voltage level determned in the Voltage
Recommended DC Operating Conditions section. This provides the reference voltage when using
HSTL class inputs. If HSTL class inputs are not being used, this pin must be connected to GND.
TDI
(3)
JTAG Test Data
Input
TDO
(3)
JTAG Test Data
Output
TMS
(3)
JTAG Mode Select
TRST
(3)
JTAG Reset
WCLK0/1/2/3
Write Clock 0/1/2/3
WCS
0/1/2/3
Write Chip Select
WDDR
Write Port DDR
WEN
0/1/2/3
V
CC
V
DDQ
GND
Vref
Symbol
Name
I/O Type
Description
PIN DESCRIPTIONS (CONTINUED)
NOTES:
1. All unused outputs may be left floating.
2. All CMOS pins should remain unchanged. CMOS format means that the pin is intended to be tied directly to V
CC
or GND and these particular pins are not tested for V
IH
or V
IL
.
3. These pins are for the JTAG port. Please refer to pages 27-31 and Figures 7-9.
相關(guān)PDF資料
PDF描述
IDT72T54252 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54252L5BB 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54252L5BBI 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54262 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72V261LA 3.3 VOLT CMOS SuperSync FIFO
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