參數(shù)資料
型號(hào)： IDT72T54242L5BBI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： DRAM
英文描述： 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
中文描述： 128K X 10 OTHER FIFO, 3.6 ns, PBGA324
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
文件頁(yè)數(shù)： 8/56頁(yè)
文件大小： 555K
代理商： IDT72T54242L5BBI
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
PAF
0/1/2/3
(Continued)
PD
Programmable
Almost-Full Flags0-3 OUTPUT
(1)
Power Down
HSTL-LVTTL This flag can operate in synchronous or asynchronous mode depending on the sate of the PFMpin
during master reset. If Dual mode is selected
PAF
1 and
PAF
3 are not used and can be left floating.
HSTL-LVTTL This input provides considerable power saving in HSTL/eHSTL mode. If this pin is low, the input
INPUT
level translators for all the data input pins, clocks and non-essential control pins are turned off.
When
PD
is brought high, power-up sequence timng will have to be adhered to before the inputs
will be recognized. It is essential that the user respect these conditions when powering down the
part and powering up the part, so as to not produce runt pulses or glitches on the clocks if the clocks
are free running.
PD
does not provide any power consumption savings when the inputs are
configured for LVTTL.
CMOS
(2)
During master reset, a HIGH on PFMselects synchronous
PAE
/
PAF
flag timng, a Low during
INPUT
master reset selects asynchronous
PAE
/
PAF
flag timng. This pin controls all
PAE
/
PAF
flag outputs.
HSTL-LVTTL These are the partial reset inputs for each internal FIFO. The read, write, flag pointers, and output
INPUT
registers will all be set to zero when partial reset is activated. During partial reset, the existing mode
(IDT or FWFT), input/output bus width and rate mode, and the programmable flag settings are all
retained. If Dual mode is selected,
PRS
1 and
PRS
3 are not used and should be tied to V
CC
.
HSTL-LVTTL These are the Data Outputs for the device. Data is read fromthe part via these outputs using the
OUTPUT
(1)
respective read port clocks and enables. In Quad mode, these outputs provide four separate busses
fromthe four separate FIFO's. Q[9:0] is FIFO[0], Q[19:10] is FIFO[1], Q[29:20] is FIFO[2], Q[39:30]
is FIFO[3]. In Dual mode these outputs provide two separate busses fromthe two separate FIFO's.
Q[19:0] is FIFO[0] and Q[39:20] is FIFO[2].
Read Clock 0/1/2/3 HSTL-LVTTL These are the clock inputs corresponding to each of the four FIFOs on the read port. If Dual mode
INPUT
is selected then RCLK1 and RCLK3 are not used and should be tied to GND. In SDR mode data
will be accessed on the rising edge of RCLK when
REN
and
RCS
are LOW at the rising edge of RCLK.
In DDR mode data will be accessed on both rising and falling edge of RCLK when
REN
is LOW.
Read Chip Select
HSTL-LVTTL These are the read chip select inputs corresponding to each of the four FIFOs on the read port. This
INPUT
pin provides synchronous control of the read port and high impedance control of the output data bus.
RCS
is only sampled on the rising edge of RCLK. During master or partial reset this input is a dont
care, if
OE
is LOW the data inputs will be in Low-Impedance regardless of the state of
RCS
. If Dual
mode is selected then
RCS
1 and
RCS
3 are not used and should be tied to V
CC
.
Read Enable
HSTL-LVTTL These are the read enable inputs corresponding to each of the four FIFOs on the read port. In SDR,
INPUT
when this signal (and
RCS
) are LOW data will be sent fromthe FIFO memory to the output bus on
every rising edge of RCLK. In DDR mode, data will be accessed on both rising and falling edges
of RCLK. Note in DDR mode the
REN
and
RCS
are only sampled on the rising edge of RCLK. New
data will always begin fromthe rising edge not the falling edge of RCLK. If Dual mode is selected
then
REN
1 and
REN
3 are not used and should be tied to V
CC
.
Read Port DDR
CMOS
(2)
During master reset, this pin selects the output port to operate in DDR or SDR format. If RDDR is HIGH,
INPUT
then a word is read on the rising and falling edge of the appropriate RCLK0, 1, 2 and 3 input. If RDDR
is LOW, then a word is read only on the rising edge of the appropriate RCLK0, 1, 2 and 3 inputs.
Serial Clock
HSTL-LVTTL Serial clock for writing and reading the
PAE
and
PAF
offset registers. On the rising edge of each
INPUT
SCLK, when
SWEN
is low, one bit of data is shifted into the
PAE
and
PAF
registers. On the rising edge
of each SCLK, when
SREN
is low, one bit of data is shifted out of the
PAE
and
PAF
offset registers.
The reading of the
PAE
and
PAF
registers is non-destructive. If programmng of the
PAE
/
PAF
offset
registers are done via the JTAG port, this input must be tied to V
CC
.
Serial Data
LVTTL
This output is used to read data fromthe programmable flag offset registers. It is used in conjunction
OUTPUT
(1)
with the
SREN
and SCLK signals.
Serial Read Enable HSTL-LVTTL When
SREN
is brought LOW before the rising edge of SCLK, the contents of the
PAE
and
PAF
INPUT
offset registers are copied to a serial shift register. While
SREN
is maintained LOW, on each rising
edge of SCLK, one bit of data is shifted out of this serial shift register through the SDO output pin.
If programmng of the
PAE
/
PAF
offset registers is done via the JTAG port, this input must be tied HIGH.
Serial Write Enable
HSTL-LVTTL On each rising edge of SCLK when
SWEN
is LOW, data fromthe FWFT/SI pin is serially loaded
INPUT
into the
PAE
and
PAF
registers. If programmng of the
PAE
/
PAF
offset registers is done via the
JTAG port, this input must be tied HIGH.
PFM
Programmable
Flag Mode
Partial Reset
PRS
0/1/2/3
Q[39:0]
Data Output Bus
RCLK0/1/2/3
RCS
0/1/2/3
REN
0/1/2/3
RDDR
SCLK
SDO
SREN
SWEN
Symbol
Name
I/O Type
Description
PIN DESCRIPTIONS (CONTINUED)
相關(guān)PDF資料
PDF描述
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IDT72T54242L6-7BBI 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
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