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參數(shù)資料
| 型號： | IDT72T54252L5BB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| 中文描述： | 64K X 20 OTHER FIFO, 3.6 ns, PBGA324 |
| 封裝： | 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324 |
| 文件頁數(shù)： | 25/56頁 |
| 文件大?。?/td> | 555K |
| 代理商： | IDT72T54252L5BB |
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25
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
chip selects (
RCS
1 and
RCS
3) should be tied to V
CC
. Refer to Figures 23 and
24,
Read Cycle and Read Chip Select
for the associated timng diagrams.
READ DOUBLE DATA RATE (RDDR)
When the read double data rate (RDDR) pin tied HIGH, the read port will be
set to double data rate mode. In this mode, all read operations are based on
the rising and falling edge of the read clocks, provided that read enables and
read chip selects are LOW. In double data rate the read enable signals are
sampled with respect to the rising edge of read clock only, and a word will be
read fromboth the rising and falling edge of read clock regardless of whether
or not read enable and read chip select are active on the falling edge of read
clock.
When RDDR is tied LOW, the read port will be set to single data rate mode.
In this mode, all read operations are based on only the rising edge of the read
clocks, provided that read enables and read chip selects are LOW during the
rising edge of read clock. This pin should be tied HIGH or LOW and cannot toggle
before or after master reset.
OUTPUT ENABLE (
OE
0/1/2/3)
There are total of four asynchronous output enables (two in Dual mode)
available in this device, each corresponding to an individual FIFO in memory.
When the output enable inputs are LOW, the output bus of each individual FIFO
becomes active and drives the data currently in the output register. When the
output enable inputs are HIGH, the output bus of each individual FIFO goes into
high-impedance. During master or partial reset the output enable is the only input
that can place the output data bus into high-impedance. During reset the read
chip select input has no effect on the output data bus. Each output enable input
is completely independent fromthe others. In Dual mode, the unused output
enables (
OE
1 and
OE
3) should be tied to V
CC
.
I/O SELECT (IOSEL)
The inputs and outputs of this device can be configured for either LVTTL or
HSTL/eHSTL operation. If the IOSEL pin is HIGH during master reset, then all
applicable LVTTL or HSTL signals will be configured for HSTL/eHSTL
operating voltage levels. To select between HSTL or eHSTL V
REF
must be
driven to 1.5V or 1.8V respectively. If the IOSEL pin is LOW during master reset,
then all applicable LVTTL or HSTL programmable pins will be configured for
LVTTL operating voltage levels. In this configuration V
REF
should be set to
GND. This pin should be tied HIGH or LOW and cannot toggle before or after
master reset. Please refer to table 5 for a list of LVTTL/HSTL/eHSTL program-
mable pins.
POWER DOWN (PD)
This device has a power down feature intended for reducing power
consumption for HSTL/eHSTL configured inputs when the device is idle for a
long period of time. By entering the power down state certain inputs can be
disabled, thereby significantly reducing the power consumption of the part. All
WEN
and
REN
signals must be disabled for a mnimumof four WCLK and RCLK
cycles before activating the power down signal. The power down signal is
asynchronous and needs to be held LOW throughout the desired power down
time. During power down, the following conditions for the inputs/outputs signals
are:
All data in FIFO(s) memory are retained.
All data inputs become inactive.
All write and read pointers maintain their last value before power down.
All enables, chip selects, and clock input pins become inactive.
All data outputs become inactive and enter high-impedance state.
All flag outputs will maintain their current states before power down.
All programmable flag offsets maintain their values.
All echo clocks and enables will become inactive and enter high-
impedance state.
The serial programmng and JTAG port will become inactive and enter
high-impedance state.
All setup and configuration CMOS static inputs are not affected, as these
pins are tied to a known value and do not toggle during operation.
All internal counters, registers, and flags will remain unchanged and maintain
their current state prior to power down. Clock inputs can be continuous and free-
running during power down, but will have no affect on the part. However, it is
recommended that the clock inputs be low when the power down is active. To
exit power down state and resume normal operations, disable the power down
signal by bringing it HIGH. There must be a mnimumof 1
μ
s waiting period before
read and write operations can resume. The device will continue fromwhere it
had stopped and no formof reset is required after exiting power down state. The
power down feature does not provide any power savings when the inputs are
configured for LVTTL operation. However, it will reduce the current for I/Os that
are not tied directly to V
CC
or GND. See Figure 35,
Power Down Operation,
for the associated timng diagram
SERIAL CLOCK (SCLK)
The serial clock is used to load and read data in the programmable offset
registers. Data fromthe serial input signal (FWFT/SI) can be loaded into the offset
registers on the rising edge of SCLK provided that the serial write enable
(
SWEN
) signal is LOW. Data can be read fromthe offset registers via the serial
data output (SDO) signal on the rising edge of SCLK provided that
SREN
is LOW.
The serial clock can operate at a maximumfrequency of 10MHz.
SERIAL WRITE ENABLE (
SWEN
)
The serial write enable input is an enable used for serial programmng of the
programmable offset registers. It is used in conjunction with the serial input
(FWFT/SI) and serial clock (SCLK) when programmng the offset registers.
When the serial write enable is LOW, data at the serial input is loaded into the
offset register, one bit for each LOW-to-HIGH transition of SCLK. When serial
write enable is HIGH, the offset registers retain the previous settings and no
offsets are loaded. Serial write enable functions the same way in both Standard
IDT and FWFT modes. See Figure 29,
Loading of Programmable Flag
Registers,
for the timng diagram
SERIAL READ ENABLE (
SREN
)
The serial read enable input is an enable used for reading the value of the
programmable offset registers. It is used in conjunction with the serial data output
(SDO) and serial clock (SCLK) when reading the offset registers. When the
serial read enable is LOW, data at the serial data output can be read fromthe
offset register, one bit for each LOW-to-HIGH transition of SCLK. When serial
read enable is HIGH, the reading of the offset registers will stop. Whenever serial
read enable (
SREN
) is activated (LOW) values in the offset registers are copied
directly into a serial scan out register.
SREN
must be kept LOW in order to read
the entire contents of the scan out register. If at any point
SREN
is toggled HIGH,
another copy function fromthe offset register to the serial scan out register will
occur the next time
SREN
is enabled (LOW). Serial read enable functions the
same way in both IDT Standard and FWFT modes. See Figure 30,
Reading
of Programmable Flag Registers,
for the timng diagram
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| IDT72T54252L6-7BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54252L6-7BBI | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54262L5BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54262L5BBG | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
| IDT72T54262L6-7BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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