參數(shù)資料
型號： IDT72T54252L5BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
中文描述： 64K X 20 OTHER FIFO, 3.6 ns, PBGA324
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
文件頁數(shù)： 20/56頁
文件大?。?/td> 555K
代理商： IDT72T54252L5BB
20
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags
OR
,
IR
,
PAE
, and
PAF
operate in the manner
outlined in Table 4,
Status Flags for FWFT Mode
. To write data into to the FIFO,
WEN
, and
WCS
must be LOW. Data presented to the DATA IN lines will be
clocked into the FIFO on subsequent transitions of WCLK. After the first write is
performed, the Output Ready (
OR
) flag will go LOW. Subsequent writes will
continue to fill up the FIFO.
PAE
will go HIGH after n + 2 words have been loaded
into the FIFO, where n is the empty offset value. The default setting for these
values are listed in Table 4,
Status Flags for FWFT Mode
. This parameter is
also user programmable as described in the Serial Writing and Reading of Offset
Registers section.
Continuing to write data into the FIFO without performng read operations will
cause the Programmable Almost-Full flag (
PAF
) to go LOW. Again, if no reads
are performed, the
PAF
will go LOW after (32,769-m writes for the IDT72T54242,
(65,537-m writes for the IDT72T54252, and (131,073-m writes for the
IDT72T54262.
In x20 dual mode,
PAF
will go LOW after (16,385-m writes for
the IDT72T54242, (32,769-m writes for the IDT72T54252, and (65,537-m
writes for the IDT72T54262.
The offset “m” is the full offset value. The default
setting for these values are listed in Table 4,
Status Flags for FWFT Mode
. This
parameter is also user programmable. See the section on serial writing and
reading of offset registers for details.
When the FIFO is full, the Input Ready (
IR
) will go LOW, inhibiting further write
operations. If no reads are performed after a reset,
IR
will go LOW after D writes
to the FIFO, where D = 32,769 writes for the IDT72T54242, 65,537 writes for
the IDT72T54252, and 131,073 writes for the IDT72T54262.
In x20 dual mode,
FF
will go LOW after 16,385 writes for the IDT72T54242, 32,769 writes for the
IDT72T54252, and 65,537 writes for the IDT72T54262.
If the FIFO is full, the first read operation will cause
IR
to go HIGH. Subsequent
read operations will cause
PAF
to go HIGH at the conditions described in Table
4,
Status Flags for FWFT Mode
. If further read operations occur without write
operations,
PAE
will go LOW when there are n words in the FIFO, where n is
the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read fromthe FIFO, the
OR
will
go HIGH inhibiting further read operations.
REN
is ignored when the FIFO is
empty, but
RCS
will continue to determne whether or not the output is in high-
impedance.
When configured in FWFT mode, the
OR
flag output is triple register-buffered
and the
IR
flag output is double register-buffered. Relevant timng diagrams for
FWFT mode can be found in Figure 19, 20, 21, 22 and 24.
6158 drw09
0
1 to n
16,384
FF
PAF PAE
EF
H
H
L
H
H
L
H
H
L
L
H
H
IDT72T54242
Dual mode
IW/OW = x20
Number of
Words in
FIFO
IDT72T54242
Quad mode or Dual mode
IW/OW = x10
or
IDT72T54252
Dual mode IW/OW = x20
IDT72T54252
Quad mode or Dual mode
IW/OW = x10
or
IDT72T54262
Dual mode IW/OW = x20
IDT72T54262
Quad mode or Dual mode
IW/OW = x10
16,384 - (m) to 16,383
0
1 to n
32,768
32,768 - (m) to 32,767
0
1 to n
65,536
65,536 - (m) to 65,535
0
1 to n
131,072
131,072 - (m) to 131,071
H
H
L
L
0
1 to n+1
16,385
IR
PAF PAE
OR
L
H
L
L
L
L
H
L
H
L
H
L
IDT72T54242
Dual mode
IW/OW = x20
Number of
Words in
FIFO
IDT72T54242
Quad mode or Dual mode
IW/OW = x10
or
IDT72T54252
Dual mode IW/OW = x20
IDT72T54252
Quad mode or Dual mode
IW/OW = x10
or
IDT72T54262
Dual mode IW/OW = x20
IDT72T54262
Quad mode or Dual mode
IW/OW = x10
16,385 - (m) to 16,384
0
1 to n+1
32,769
32,769 - (m) to 32,768
0
1 to n+1
65,537
65,537 - (m) to 65,536
0
1 to n+1
131,073
131,073 - (m) to 131,072
L
H
L
H
NOTE:
1. See Table 2 for values for n, m Values n,mmay be different for each FIFO.
NOTE:
1. See Table 2 for values for n, m Values n,mmay be different for each FIFO.
TABLE 3 — STATUS FLAGS FOR IDT STANDARD MODE
TABLE 4 — STATUS FLAGS FOR FWFT MODE
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IDT72T54252L6-7BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54252L6-7BBI 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54262L5BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54262L5BBG 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:是 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54262L6-7BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
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