參數(shù)資料
型號(hào)： IDT72T54252L5BB
廠(chǎng)商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： DRAM
英文描述： 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
中文描述： 64K X 20 OTHER FIFO, 3.6 ns, PBGA324
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
文件頁(yè)數(shù)： 18/56頁(yè)
文件大?。?/td> 555K
代理商： IDT72T54252L5BB
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
SERIAL WRITING AND READING OF OFFSET REGISTERS
The offset registers can be loaded with a default value or they can be user
programmed with a specific value. One of four default values are loaded based
on the state of the FSEL[1:0] inputs. The flag offset values can be programmed
either through the dedicated serial programmng port or the JTAG port. The
dedicated serial port can be used to load or read the contents of the offset
registers. The offset registers are programmed and read sequentially through
a series of shift registers.
Each bit in the serial input will shift through the offset
registers and programeach FIFOs offset registers.
The serial read and write operations are performed by the dedicated SCLK,
FWFT/SI,
SWEN
,
SREN
and SDO pins.
The total number of bits required per
device are listed in Figure 3,
Programmable Flag Offset Programmng
Methods
.
These bits account for all four
PAE
/
PAF
offset registers in the device.
To write to the offset registers, set the serial write enable signal active (LOW),
and on each rising edge of SCLK one bit fromthe FWFT/SI pin is serially shifted
into the flag offset register chain.
Once the complete number of bits has been
programmed into all four registers, the programmng sequence is complete.
The
programmng sequence is listed in Figure 3.
To read the values fromthe offset
registers, set the serial read enable active (LOW). Then on each rising edge
of SCLK, one bit is shifted out to the serial data output. The serial read enable
must be kept LOW throughout the entire read operation. To stop reading the offset
register, disable the serial read enable (HIGH).
There is a setup time for reading
the offset registers, as the offset register data for each FIFO is temporarily stored
in a scan chain. When data has been completely read out of the offset registers,
any additional read operations to the offset register will result in zeros as the
output data.
Reading and writing the offset registers can also be accomplished using the
JTAG port.
To write to the offset registers using JTAG, set the instructional register
to the offset write command (Hex Value = 0x0008).
The JTAG port will load data
into each of the offset registers in a simlar fashion as the serial programmng
described above.
To read the values fromthe offset registers, set the instructional
register to the offset read command (Hex Value = 0x0007).
The TDO of the JTAG
port will output data in a simlar fashion as the serial programmng described
above.
The number of bits required to load the offset registers is dependent on the
size of the device selected and the width of the I/Os selected. Each offset register
requires 15 bits, 16 bits or 17 bits for the IDT72T54242/72T54252/72T54262
devices respectively. So a total of 120 bits, 128 bits or 136 bits will need to be
loaded into each offset register chain for the IDT72T54242/72T54252/72T54262
devices respectively. If Dual mode is selected, only two of the four offset register
will need to be programmed (
PAE
/
PAF
2,
PAE
/
PAF
0). Therefore, the total
number of bits required will be half of its Quad mode operation. See Figure 4,
Offset Register Serial Bit Sequence
for a mapping of the serial bits to each offset
registers.
6158 drw07
0008 (Hex)
Serial Programming
JTAG Programming
Instruction Code
IDT Part Number
0
1
IDT72T54242
IDT72T54252
IDT72T54262
SWEN
SREN
1
0
0007 (Hex)
IDT72T54242
IDT72T54252
IDT72T54262
Quad Mode
120
128
136
120
128
136
Dual Mode
(4)
(IW/OW = x10)
60
64
68
60
64
68
Dual Mode
(IW/OW = x20)
56
60
64
56
60
64
PROGRAMMING INSTRUCTIONS:
J TAG Programming
1. Load JTAG Instruction code in "JTAG Timng Specifications" section.
2. Use rising edge of TCK to clock in the required bits fromthe TD2 input or to clock out fromthe TDO output pin.
Serial Programming
1. Set
SWEN
and
SREN
as shown above.
2. If reading,
SREN
LOW will clock data out of the SDO pin on every rising TCK edge. If writing,
SWEN
LOW will clock in data fromthe FWFT/SI pin.
NOTES:
1. The programmng methods apply to both IDT Standard mode and FWFT mode.
2. The number of bits indicated are for all four
PAE
/
PAF
offset registers.
3.
SWEN
= 0, and
SREN
= 0 simultaneously are not allowed.
4. In Dual mode (IW/OW = x10), the total number of bits required will be half since only two FIFOs are active.
5. Parallel programmng is not available.
Figure 3. Programmable Flag Offset Programming Methods
相關(guān)PDF資料
PDF描述
IDT72T54252L5BBI 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54262 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72V261LA 3.3 VOLT CMOS SuperSync FIFO
IDT72V85L15PAG 3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO
IDT72V85L15PAGI 3.3 Volt CMOS DUAL ASYNCHRONOUS FIFO
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72T54252L6-7BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪(fǎng)問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
IDT72T54252L6-7BBI 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪(fǎng)問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
IDT72T54262L5BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪(fǎng)問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
IDT72T54262L5BBG 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:是 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪(fǎng)問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
IDT72T54262L6-7BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲(chǔ)容量:256（64 x 4） 數(shù)據(jù)速率:- 訪(fǎng)問(wèn)時(shí)間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱(chēng):74F433
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*