參數(shù)資料
型號： IDT72T54262L5BBI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
中文描述： 512K X 10 OTHER FIFO, 3.6 ns, PBGA324
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
文件頁數(shù)： 14/56頁
文件大?。?/td> 555K
代理商： IDT72T54262L5BBI
14
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
(1)
(Commercial: V
CC
= 2.5V ± 0.15V, T
A
= 0
°
C to +70
°
C;Industrial: V
CC
= 2.5V ± 0.15V, T
A
= -40
°
C to +85
°
C; JEDEC JESD8-A compliant)
Commerical
IDT72T54242L5
IDT72T54252L5
IDT72T54262L5
Min.
Com'l & Ind'l
IDT72T54242L6-7
IDT72T54252L6-7
IDT72T54262L6-7
Min.
Symbol
Parameter
Max.
Max.
Unit
f
S1
f
S2
t
A
t
CLK1
t
CLK2
t
CLKH1
t
CLKH2
t
CLKL1
t
CLKL2
t
DS
t
DH
t
ENS
t
ENH
f
C
t
ASO
t
SCLK
t
SCKH
t
SCKL
t
SDS
t
SDH
t
SENS
t
SENH
t
RS
(3)
t
RSS
t
RSR
t
RSF
t
OLZ
(
OE
- Qn)
t
OHZ
t
OE
t
RCSLZ
t
RCSHZ
t
PDLZ
t
PDHZ
t
PDL
t
PDH
t
WFF
t
REF
t
PAFS
t
PAES
t
PAFA
t
PAEA
t
ERCLK
t
CLKEN
t
SKEW1
t
SKEW2
t
SKEW3
NOTES:
1. With exception to clock cycle frequency, these parameters apply to both DDR and SDR modes of operation.
2. All AC timngs apply to both IDT Standard mode and FWFT mode in both Quad and Dual mode.
3. Pulse width less than the mnimumvalue is not allowed.
4. Values guaranteed by design, not currently tested.
5. Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades available by special order.
Clock Cycle Frequency (WCLK & RCLK) SDR
Clock Cycle Frequency (WCLK & RCLK) DDR
Data Access Time
Clock Cycle Time SDR
Clock Cycle Time DDR
Clock High Time SDR
Clock High Time DDR
Clock Low Time SDR
Clock Low Time DDR
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Clock Cycle Frequency (SCLK)
Serial Output Data Access Time
Serial Clock Cycle
Serial Clock High
Serial Clock Low
Serial Data In Setup
Serial Data In Hold
Serial Enable Setup
Serial Enable Hold
Reset Pulse Width
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Impedance
Output Enable to Output in High-Impedance
Output Enable to Data Output Valid
RCLK to Active fromHigh-Impedance
RCLK to High-Impedance
Power Down to Output Low-Impedance
Power Down to Output High-Impedance
Power Down LOW
Power Down HIGH
Write Clock to
FF
or
IR
Read Clock to
EF
or
OR
Write Clock to Synchronous Programmable Almost-Full Flag
Read Clock to Synchronous Programmable Almost-Empty Flag
Write Clock to Asynchronous Programmable Almost-Full Flag
Read Clock to Asynchronous Programmable Almost-Empty Flag
RCLK to Echo RCLK Output
RCLK to Echo
REN
Output
SKEW time between RCLK and WCLK for
EF
/
OR
and
FF
/
IR
for SDR inputs and outputs
SKEW time between RCLK and WCLK for
EF
/
OR
and
FF
/
IR
in for DDR inputs and outputs
SKEW time between RCLK and WCLK for
PAE
and
PAF
—
—
0.6
5
10
2.3
4.5
2.3
4.5
1.5
0.5
1.5
0.5
—
—
100
45
45
15
5
5
5
200
15
10
—
0.6
0.6
0.6
—
—
—
—
—
1
—
—
—
—
—
—
—
—
4
5
5
200
100
3.6
—
—
—
—
—
—
—
—
—
—
10
20
—
—
—
—
—
—
—
—
—
—
12
3.6
3.6
3.6
3.6
3.6
19.4
13.5
19.4
—
3.6
3.6
3.6
3.6
10
10
4.0
3.6
—
—
—
—
—
0.6
6.7
13
2.8
6.0
2.8
6.0
2.0
0.5
2.0
0.5
—
—
100
45
45
15
5
5
5
200
15
10
—
0.8
0.8
0.8
—
—
—
—
—
1
—
—
—
—
—
—
—
—
5
6
6
150
75
3.8
—
—
—
—
—
—
—
—
—
—
10
20
—
—
—
—
—
—
—
—
—
—
15
3.8
3.8
3.8
3.8
3.8
19.6
13.7
19.6
—
3.8
3.8
3.8
3.8
12
12
4.3
3.8
—
—
—
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μ
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
相關(guān)PDF資料
PDF描述
IDT72T54242 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54242L5BB 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54242L5BBI 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54252 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54252L5BB 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72T54262L6-7BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54262L6-7BBI 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T55248L5BB 功能描述:IC CTRL QUADMUX FLOW 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT72T55248L6-7BB 功能描述:IC CTRL QUADMUX FLOW 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT72T55248L6-7BBI 功能描述:IC CTRL QUADMUX FLOW 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
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