參數(shù)資料
型號： IDT72T54262L5BBI
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
中文描述： 512K X 10 OTHER FIFO, 3.6 ns, PBGA324
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
文件頁數(shù)： 19/56頁
文件大小： 555K
代理商： IDT72T54262L5BBI
19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72T54242/72T54252/72T54262 support two different timng modes
of operation: IDT Standard mode and First Word Fall Through (FWFT) mode.
The selection of which mode will be used is determned during master reset, by
the state of the FWFT input.
During master reset, if the FWFT pin is LOW, then IDT Standard mode will
be selected. This mode uses the Empty Flag (
EF
) to indicate whether or not there
are any words present in the FIFO. It also uses the Full Flag (
FF
) to indicate
whether or not the FIFO has any free space for writing. In IDT Standard mode,
every word read fromthe FIFO, including the first, must be requested using the
Read Enable (
REN
), Read Chip Select (
RCS
), and RCLK.
If the FWFT pin is HIGH during master reset, then FWFT mode will be
selected. This mode uses Output Ready (
OR
) to indicate whether or not there
is valid data at the data outputs.
It also uses Input Ready (
IR
) to indicate whether
or not the FIFO has any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes directly to output bus after three RCLK rising
edges. Applying
REN
= LOW is not necessary, although having
RCS
= 0 at the
previous rising RCLK is necessary to keep the output frombeing in high-
impedance. However, subsequent words must be accessed using Read
Enable (
REN
), Read Chip Select (
RCS
), and RCLK.
Various signals in both
inputs and outputs operate differently depending on which timng mode is in effect.
The timng mode selected affects all internal FIFOs and are not programmed
individually.
IDT STANDARD MODE
In this mode, the status flags
FF
,
PAF
,
PAE
, and
EF
operate in the manner
outlined in Table 3,
Status Flags for IDT Standard Mode
. To write data into the
FIFO, Write Enable (
WEN
), and Write Chip Select (
WCS
) must be LOW. Data
presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of the Write Clock (WCLK). After the first write is performed, the Empty
Flag (
EF
) will go HIGH. Subsequent writes will continue to fill up the FIFO. The
Programmable Almost-Empty flag (
PAE
) will go HIGH after n + 1 words have
been loaded into the FIFO, where "n" is the empty offset value. The default
settings for these values are listed in Table 2. This parameter is also user
programmable as described in the Serial Writing and Reading of Offset Registers
section.
Continuing to write data into the FIFO without performng read operations will
cause the Programmable Almost-Full flag (
PAF
) to go LOW. Again, if no reads
are performed, the
PAF
will go LOW after (32,768-m writes for the IDT72T54242,
(65,536-m writes for the IDT72T54252, and (131,072-m writes for the
IDT72T54262.
In x20 dual mode,
PAF
will go LOW after (16,384-m writes for
the IDT72T54242, (32,768-m writes for the IDT72T54252, and (65,536-m
writes for the IDT72T54262.
The offset “m” is the full offset value. The default
setting for these values are listed in Table 3,
Status Flags for IDT Standard
Mode
. This parameter is also user programmable. See the section on Serial
Writing and Reading of Offset Registers for details.
When the FIFO is full, the Full Flag (
FF
) will go LOW, inhibiting further write
operations. If no reads are performed after a reset,
FF
will go LOW after D writes
to the FIFO, where D = 32,768 writes for the IDT72T54242, 65,536 writes for
the IDT72T54252, and 131,072 writes for the IDT72T54262.
In x20 dual mode,
FF
will go LOW after 16,384 writes for the IDT72T54242, 32,768 writes for the
IDT72T54252, and 65,536 writes for the IDT72T54262.
If the FIFO is full, the first read operation will cause
FF
to go HIGH. Subsequent
read operations will cause
PAF
to go HIGH at the conditions described in Table
3,
Status Flags for IDT Standard Mode
. If further read operations occur without
write operations,
PAE
will go LOW when there are n words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read fromthe FIFO, the
EF
will
go LOW inhibiting further read operations.
REN
is ignored when the FIFO is
empty, but
RCS
will continue to determne whether or not the output is in high-
impedance.
When configured in IDT Standard mode, the
EF
and
FF
outputs are double
register-buffered outputs. IDT Standard mode is available when the device is
configured in either Single Data Rate or Double Data Rate mode. Relevant
timng diagrams for IDT Standard mode can be found in Figure 10, 11, 12, 13,
14, 15, 16, 17, 18 and 23.
6158 drw08
16 - 30
31 - 45
46 - 60
61 - 75
76 - 90
1 - 15
91 - 105
106 - 120
Serial Bits
IDT72T54252
Quad mode
IDT72T54262
Quad mode
IDT72T54242
Quad mode
IDT72T54242
Dual mode
IW/OW = x10
or
IDT72T54252
IW/OW = x20
IDT72T54252
Dual mode
IW/OW = x10
or
IDT72T54262
IW/OW = x20
IDT72T54242
Dual mode
IW/OW = x20
Offset
Register
17 - 32
33 - 48
49 - 64
65 - 80
81 - 96
1 - 16
97 - 112
113 - 128
18 - 34
35 - 51
52 - 68
69 - 85
86 - 102
1 - 17
103 - 119
120 - 136
1 - 14
15 - 28
29 - 42
43 - 56
1 - 15
16 - 30
31 - 45
46 - 60
1 - 16
17 - 32
33 - 48
49 - 64
PAE
3
(1)
PAF
3
(1)
PAE
2
PAF
2
PAE
1
(1)
PAF
1
(1)
PAE
0
PAF
0
IDT72T54262
Dual mode
IW/OW = x10
1 - 17
18 - 34
35 - 51
52 - 68
Figure 4. Offset Registers Serial Bit Sequence
NOTES:
1. These registers are not used in Dual mode. They are not programmed or read in the serial chain.
2. In all modes, the higher numbered bit is the MSB. For example, in the IDT72T54242 in Quad mode, the first bit is the LSB for
PAE
3.
相關(guān)PDF資料
PDF描述
IDT72T54242 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54242L5BB 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54242L5BBI 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54252 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54252L5BB 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72T54262L6-7BB 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T54262L6-7BBI 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標準包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433
IDT72T55248L5BB 功能描述:IC CTRL QUADMUX FLOW 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT72T55248L6-7BB 功能描述:IC CTRL QUADMUX FLOW 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT72T55248L6-7BBI 功能描述:IC CTRL QUADMUX FLOW 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
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