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| 型號： | IDT72T54262L5BBI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS |
| 中文描述： | 512K X 10 OTHER FIFO, 3.6 ns, PBGA324 |
| 封裝： | 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324 |
| 文件頁數(shù)： | 26/56頁 |
| 文件大?。?/td> | 555K |
| 代理商： | IDT72T54262L5BBI |
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26
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
OUTPUTS:
DATA OUTPUT BUS (Q[39:0])
The data output busses are 10 bits wide in Quad mode and 20 or 10-bits wide
in Dual mode. In Quad mode, Q[9:0] are data outputs for FIFO0, Q[19:10] are
for FIFO1, Q[29:20] are for FIFO2, and Q[39:30] are for FIFO3. In Dual mode,
Q[19:0] are data outputs for FIFO0 and Q[39:20] are for FIFO2 for the 20-bit
wide data bus. Q[9:0] are data outputs for FIFO0 and Q[29:20] are data outputs
for FIFO2 for the 10-bit wide data bus.
EMPTY/OUTPUT READY FLAG (
EF
/0/1/2/3)
There are four empty/output ready flags (two in Dual mode) available in this
device, each corresponding to the individual FIFOs in memory. This is a dual-
purpose pin whose function is determned based on the state of the FWFT/SI
pin during master reset. In the IDT Standard mode, the empty flags are selected.
When an individual FIFO is empty, its empty flag will go LOW, inhibiting further
read operations fromthat FIFO. When the empty flag is HIGH, the individual
FIFO is not empty and valid read operations can be performed. See Figure 18,
Read Cycle, Output Enable and Empty Flag Timng
, for the relevant timng
information. Also see Table 3,
Status Flags for IDT Standard Mode
for the truth
table of the empty flags.
In FWFT mode, the output ready flags are selected. Output ready flags (
OR
)
go LOW at the same time that the first word written to an empty FIFO appears
on the outputs, which is a mnimumof two read clock cycles provided the RCLK
and WCLK meets the t
SKEW
parameter (See Table 6 - T
SKEW
Measurement).
OR
stays LOW after the RCLK LOW-to- HIGH transitions that shifts the last word
fromthe FIFO memory to the outputs.
OR
goes HIGH when another read
operation is performed, indicating the last word was read. The previous data
stays at the outputs, further data reads are inhibited until
OR
goes LOW again
and a new word appears on the bus. See Figure 22,
Read Timng and Output
Ready Flag
, for the relevant timng information. Also see Table 4,
Status Flags
for FWFT Mode
for the truth table of the empty flags. To prevent reading in the
FWFT mode, the output ready flag of each FIFO will go HIGH with respect to
RCLK, when the total number of words has been read out of the FIFO, thus
inhibiting further read operations. Upon the completion of a valid write cycle, the
output ready flag will go LOW with respect to RCLK three cycles later, thus
indicating another read has occurred.
The empty/output ready flags are synchronous and updated on the rising
edge of RCLK. In IDT Standard mode, the flags are double register-buffered
outputs. In FWFT mode, the flags are triple register-buffered outputs. Each
empty flag operates independently of the others and always indicates the
respective FIFO’s status.
FULL/INPUT READY FLAG (
FF
/
IR
/0/1/2/3)
There are four full/input ready flags (two in Dual mode) available in this
device, each corresponding to the individual FIFOs in memory. This is a dual-
purpose pin whose function is determned based on the state of the FWFT/SI
pin during master reset. In the IDT Standard mode, the full flags are selected.
When an individual FIFO is full, its full flags will go LOW after the rising edge of
WCLK that wrote the last word, thus inhibiting further write operations to the FIFO.
When the full flag is HIGH, the individual FIFO is not full and valid write operations
can be performed. See Figure 11,
Write Cycle and Full Flag Timng
for the
associated timng diagram Also see Table 4,
Status Flags for FWFT Mode
for
the truth table of the full flags.
In FWFT mode, the input ready flags are selected. Input ready flags go LOW
when there is adequate memory space in the FIFOs for writing in data. The input
ready flags go HIGH after the rising edge of WCLK that wrote the last word, when
there are no free spaces available for writing in data. See Figure 16,
Write Cycle
and Output Ready Timng
, for the associated timng information. Also see Table
4,
Status Flags for FWFT Mode
for the truth table of the full flags. The input ready
status not only measures the contents of the FIFOs memory, but also counts the
presence of a word in the output register. Thus, in FWFT mode, the total number
of writes necessary to make
IR
LOW is one greater than needed to assert
FF
in IDT Standard mode.
FF
/
IR
is synchronous and updated on the rising edge of WCLK.
FF
/
IR
are
double register-buffered outputs. Each flag operates independently of the
others. To prevent data overflow in the IDT Standard mode, the full flag of each
FIFO will go LOW with respect to WCLK, when the maximumnumber of words
has been written into the FIFO, thus inhibiting further write operations. Upon the
completion of a valid read cycle, the full flag will go HIGH with respect to WCLK
two cycles later, thus allowing another write to occur.
To prevent data overflow in the FWFT mode, the input ready flag of each FIFO
will go HIGH with respect to WCLK, when the maximumnumber of words has
been written into the FIFO, thus inhibiting further write operations. Upon the
completion of a valid read cycle, the input ready flag will go LOW with respect
to WCLK two cycles later, thus allowing another write to occur.
PROGRAMMABLE ALMOST EMPTY FLAG (
PAE
0/1/2/3)
There are four programmable almost empty flags (two in Dual mode)
available in this device, each corresponding to an individual FIFO in memory.
The programmable almost empty flag is an additional status flag that notifies the
user when the FIFO memory is near empty. The user may utilize this feature
as an early indicator as to when the FIFO will become empty. In IDT Standard
mode,
PAE
will go LOW when there are n words or less in the FIFO. In FWFT
mode, the
PAE
will go LOW when there are n-1 words or less in the FIFO. The
offset “n” is the empty offset value. The default setting for this value is stated in
Table 2. There are four internal FIFOs hence four
PAE
offset values, (n0, n1,
n2, and n3).
There are two timng modes available for the
PAE
flags, selectable by the state
of the Programmable Flag Mode (PFM) pin. If PFMis tied HIGH, then
synchronous timng mode is selected. If PFMis tied LOW, then asynchronous
timng mode is selected. In synchronous configuration, the
PAE
flag is updated
on the rising edge of RCLK. In asynchronous
PAE
configuration, the
PAE
flag
is asserted LOW on the LOW-to-HIGH transitions of the Read Clock (RCLK).
PAE
is reset to HIGH on the LOW-to-HIGH transitions of the Write Clock (WCLK).
See Figures 31 and 33,
Synchronous and Asynchronous Programmable
Almost-Empty Flag Timng
, for the relevant timng information.
Each programmable almost empty flag operates independently of the others.
PROGRAMMABLE ALMOST FULL FLAG (
PAF
0/1/2/3)
There are four programmable almost full flags (two in Dual mode) available
in this device, each corresponding to the individual FIFOs in memory. The
programmable almost full flag is an additional status flag that notifies the user when
the FIFO memory is nearly full. The user may utilize this feature as an early
indicator as to when the FIFO will not be able to accept any more data and thus
prevent data frombeing dropped. In IDT Standard mode, if no reads are
performed after master reset,
PAF
will go LOW after (D-m (D meaning the
density of the particular device) words are written to the FIFO. In FWFT mode,
PAF
will go LOW after (D+1-m words are written to the FIFO. The offset “m”
is the full offset value. The default setting for this value is stated in Table 2. There
are four internal FIFOs hence four
PAF
offset values, (m0, m1, m2, and m3).
There are two timng modes available for the
PAF
flags, selectable by the state
of the Programmable Flag Mode (PFM) pin. If PFMis tied HIGH, then
synchronous timng mode is selected. If PFMis tied LOW, then asynchronous
timng mode is selected. In synchronous configuration, the
PAF
flag is updated
on the rising edge of WCLK. In asynchronous
PAF
configuration, the
PAF
flag
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| IDT72T54262L6-7BB | 功能描述:IC FIFO DDR/SDR QUAD/DUAL 324BGA RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72T 標(biāo)準(zhǔn)包裝:15 系列:74F 功能:異步 存儲容量:256（64 x 4） 數(shù)據(jù)速率:- 訪問時間:- 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:24-DIP（0.300"，7.62mm） 供應(yīng)商設(shè)備封裝:24-PDIP 包裝:管件 其它名稱:74F433 |
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| IDT72T55248L6-7BB | 功能描述:IC CTRL QUADMUX FLOW 324-BGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝 |
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