參數(shù)資料
型號: IDT72T54262L5BBI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
中文描述: 512K X 10 OTHER FIFO, 3.6 ns, PBGA324
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-324
文件頁數(shù): 32/56頁
文件大?。?/td> 555K
代理商: IDT72T54262L5BBI
32
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T54242/72T54252/72T54262 2.5V QUAD/DUAL TeraSync
DDR/SDR FIFO
32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2
MARCH 22, 2005
CLAMP
The optional CLAMP instruction sets the outputs of an IC to logic levels
determned by the contents of the boundary-scan register and selects the one-
bit bypass register to be connected between TDI and TDO. Before loading this
instruction, the contents of the boundary-scan register can be preset with the
SAMPLE/PRELOAD instruction. During this instruction, data can be shifted
through the bypass register fromTDI to TDO without affecting the condition of
the outputs.
HIGH-IMPEDANCE
The optional High-Impedance instruction sets all outputs (including two-state
as well as three-state types) of an IC to a disabled (high-impedance) state and
selects the one-bit bypass register to be connected between TDI and TDO.
During this instruction, data can be shifted through the bypass register fromTDI
to TDO without affecting the condition of the IC outputs.
OFFSET READ
This instruction is an alternative to serial reading the offset registers for the
PAE
/
PAF
flags. When reading the offset registers through this instruction, the
dedicated serial programmng signals must be disabled.
OFFSET WRITE
This instruction is an alternative to serial programmng the offset registers for
the
PAE
/
PAF
flags. When writing the offset registers through this instruction, the
dedicated serial programmng signals must be disabled.
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
functional mode and selects the one-bit bypass register to be connected
between TDI and TDO. The BYPASS instruction allows serial data to be
transferred through the IC fromTDI to TDO without affecting the operation of
the IC.
相關(guān)PDF資料
PDF描述
IDT72T54242 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54242L5BB 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54242L5BBI 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54252 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
IDT72T54252L5BB 2.5V QUAD/DUAL TeraSync⑩ DDR/SDR FIFO x10 QUAD FIFO or x10/x20 DUAL FIFO CONFIGURATIONS
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