參數(shù)資料
型號: IDT72V3643L10PF8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/28頁
文件大?。?/td> 0K
描述: IC SYNCFIFO 1024X36 10NS 128TQFP
標準包裝: 1,000
系列: 72V
功能: 異步,同步
存儲容量: 36.8K(1K x 36)
數(shù)據(jù)速率: 100MHz
訪問時間: 10ns
電源電壓: 3 V ~ 3.6 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 帶卷 (TR)
其它名稱: 72V3643L10PF8
1
2010
Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4662/6
MAY 2010
3.3 VOLT CMOS SyncFIFOTM WITH
BUS-MATCHING
256 x 36 , 512 x 36
1,024 x 36
IDT72V3623
IDT72V3633
IDT72V3643
IDT and the IDT logo are registered trademark of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
FEATURES:
Memory storage capacity:
IDT72V3623–256 x 36
IDT72V3633–512 x 36
IDT72V3643–1,024 x 36
Clock frequencies up to 100 MHz (6.5 ns access time)
Clocked FIFO buffering data from Port A to Port B
IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions)
Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64)
Serial or parallel programming of partial flags
Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte)
Big- or Little-Endian format for word and byte bus sizes
Reset clears data and configures FIFO, Partial Reset clears data
but retains configuration settings
Mailbox bypass registers for each FIFO
Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
Easily expandable in width and depth
Auto power down minimizes power dissipation
Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)
Pin and functionally compatible versions of the 5V operating
IDT723623/723633/723643
Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
Mail 1
Register
Programmable Flag
Offset Registers
Status Flag
Logic
EF/OR
AE
36
FF/IR
AF
36
Timing
Mode
FWFT
A0-A35
SPM
FS0/SD
FS1/SEN
B0-B35
Write
Pointer
Read
Pointer
Mail 2
Register
MBF2
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
Port-B
Control
Logic
10
4662 drw01
Input
Register
RAM ARRAY
256 x 36
512 x 36
1,024 x 36
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
FIFO1
Mail1,
Mail2,
Reset
Logic
RS1
MBF1
36
Bus-
Matching
Output
Register
PRS
36
RS2
36
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