- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10001 > IDT72V3643L10PF8 (IDT, Integrated Device Technology Inc)IC SYNCFIFO 1024X36 10NS 128TQFP PDF資料下載
參數(shù)資料
| 型號： | IDT72V3643L10PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 24/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNCFIFO 1024X36 10NS 128TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 72V |
| 功能： | 異步，同步 |
| 存儲容量： | 36.8K（1K x 36） |
| 數(shù)據(jù)速率： | 100MHz |
| 訪問時間： | 10ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V3643L10PF8 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁
5
COMMERCIAL TEMPERATURERANGE
IDT72V3623/72V3633/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING
256 x 36, 512 x 36, 1,024 x 36
Symbol
Name
I/O
Description
PIN DESCRIPTIONS (CONTINUED)
MBA
Port A Mailbox
I
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
Select
MBB
Port B Mailbox
I
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the
Select
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output and
a LOW level selects FIFO data for output.
MBF1
Mail1 Register Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while
MBF1 is LOW. MBF1 is set HIGH by a LOW-to-
HIGH transition of CLKB when a Port B read is selected and MBB is HIGH.
MBF1 is set HIGH
following either a Reset (
RS1) or Partial Reset (PRS).
MBF2
Mail2 Register Flag
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.
Writes to the mail2 register are inhibited while
MBF2 is LOW. MBF2 is set HIGH by a LOW-to-
HIGH transition of CLKA when a Port A read is selected and MBA is HIGH.
MBF2 is set HIGH
following either a Reset (
RS2) or Partial Reset (PRS).
RS1, RS2
Resets
I
A LOW on both pins initializes the FIFO read and write pointers to the first location of memory and
sets the Port B output register to all zeroes. A LOW-to-HIGH transition on
RS1selectstheprogramming
method (serial or parallel) and one of three programmable flag default offsets. It also configures Port
B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-
HIGH transitions of CLKB must occur while
RS1 is LOW.
PRS
PartialReset
I
A LOW on this pin initializes the FIFO read and write pointers to the first location of memory and sets
the Port B output register to all zeroes. During Partial Reset, the currently selected bus size, endian
arrangement,programmingmethod(serialorparallel),andprogrammableflagsettingsareallretained.
SIZE
Bus Size Select
I
A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin
(Port B)
when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size
and endian arrangement for Port B. The level of SIZE must be static throughout device operation.
SPM
Serial Programming
I
A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel
Mode
programming or default offsets (8, 16, or 64).
W/
RA
Port A Write/
I
A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH
Read Select
transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/
RA is HIGH.
W/RB
Port B Write/
I
A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH
Read Select
transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when
W/RB is LOW.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MS27484E20B41P | CONN PLUG 41POS STRAIGHT W/PINS |
| IDT723626L15PF8 | IC FIFO SYNC 256X36X2 128QFP |
| MS27468T19F32S | CONN RCPT 32POS JAM NUT W/SCKT |
| D38999/24WD5SD | CONN RCPT 5POS JAM NUT W/SCKT |
| IDT723624L15PF8 | IC FIFO SYNC 256X36X2 128QFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT72V3643L15PF | 功能描述:IC SYNCFIFO 1024X36 15NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3643L15PF8 | 功能描述:IC SYNCFIFO 1024X36 15NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3644L10PF | 功能描述:IC FIFO 2048X36 10NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3644L10PF8 | 功能描述:IC FIFO 2048X36 10NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3644L15PF | 功能描述:IC FIFO 2048X36 15NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。