IDT72V3623/72V3633/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING 256 x 36, " />
參數(shù)資料
型號(hào)： IDT72V3643L10PF8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 23/28頁(yè)
文件大小： 0K
描述： IC SYNCFIFO 1024X36 10NS 128TQFP
標(biāo)準(zhǔn)包裝： 1,000
系列： 72V
功能： 異步，同步
存儲(chǔ)容量： 36.8K（1K x 36）
數(shù)據(jù)速率： 100MHz
訪問(wèn)時(shí)間： 10ns
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 帶卷 (TR)
其它名稱： 72V3643L10PF8
4
IDT72V3623/72V3633/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURERANGE
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
Port A Data
I/O
36-bit bidirectional data port for side A.
AE
Almost-EmptyFlag
O
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in
(Port B)
the FIFO is less than or equal to the value in the Almost-Empty B offset register, X.
AF
Almost-FullFlag
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty
(Port A)
locations in the FIFO is less than or equal to the value in the Almost-Full A offset register, Y.
B0-B35
Port B Data
I/O
36-bit bidirectional data port for side B.
BE/
FWFT
Big-Endian/
I
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation.
First Word
In this case, depending on the bus size, the most significant byte or word written to Port A is read
Fall Through
from Port B first. A LOW on BE will select Little-Endian operation. In this case, the least significant
byte or word written to Port A is read from Port B first. After Master Reset, this pin selects the timing
mode. A HIGH on
FWFT selects IDT Standard mode, a LOW selects First Word Fall Through
mode. Once the timing mode has been selected, the level on
FWFT must be static throughout
device operation.
BM
Bus-MatchSelect
I
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of
(Port B)
SIZE. A LOW selects long word operation. BM works with SIZE and BE to select the bus size and
endian arrangement for Port B. The level of BM must be static throughout device operation.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through Port A and can be
asynchronous or coincident to CLKB.
FF/IR and AF are synchronized to the LOW-to-HIGH
transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through Port B and can be
asynchronous or coincident to CLKA.
EF/OR and AE are synchronized to the LOW-to-HIGH
transition of CLKB.
CSA
Port A Chip
I
CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The
Select
A0-A35 outputs are in the high-impedance state when
CSA is HIGH.
CSB
Port B Chip
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
Select
The B0-B35 outputs are in the high-impedance state when
CSB is HIGH.
EF/OR
Empty/Output
O
This is a dual function pin. In the IDT Standard mode, the
EF function is selected. EFindicates
Ready Flag
whetherornottheFIFOmemoryisempty. IntheFWFTmode,the ORfunctionisselected. ORindicates
(Port B)
the presence of valid data on the B0-B35 outputs, available for reading.
EF/OR is synchronized to the
LOW-to-HIGH transition of CLKB.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
FF/IR
Full/Input
O
This is a dual function pin. In the IDT Standard mode, the
FF function is selected. FF indicates
Ready Flag
whether or not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR
(Port A)
indicates whether or not there is space available for writing to the FIFO memory.
FF/IR is
synchronized to the LOW-to-HIGH transition of CLKA.
FS1/
SEN
FlagOffset
I
FS1/
SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During
Select 1/
Reset, FS1/
SEN andFS0/SD,togetherwithSPM,selecttheflagoffsetprogrammingmethod.
Serial Enable,
Three offset register programming methods are available: automatically load one of three preset
values (8, 16, or 64), parallel load from Port A, and serial load.
FS0/SD
FlagOffset
I
Select 0/
When serial load is selected for flag offset register programming, FS1/
SEN is used as an enable
Serial Data
synchronous to the LOW-to-HIGH transition of CLKA. When FS1/
SENisLOW,arisingedgeonCLKA
CLKA load the bit present on FS0/SD into the X and Y registers. The number of bit writes required
to program the offset registers is 16 for the IDT72V3623, 18 for the IDT72V3633, and 20 for the
IDT72V3643. The first bit write stores the Y-register MSB and the last bit write stores the X-register LSB.
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