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參數(shù)資料
| 型號： | IDT72V3643L10PF8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNCFIFO 1024X36 10NS 128TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | 72V |
| 功能： | 異步，同步 |
| 存儲容量： | 36.8K（1K x 36） |
| 數(shù)據(jù)速率： | 100MHz |
| 訪問時間： | 10ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-LQFP |
| 供應(yīng)商設(shè)備封裝： | 128-TQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 72V3643L10PF8 |
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13
COMMERCIAL TEMPERATURERANGE
IDT72V3623/72V3633/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING
256 x 36, 512 x 36, 1,024 x 36
forcing the Empty Flag HIGH; only then can data be read.
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing
clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 11 and 12).
FULL/INPUT READY FLAGS (
FF/IR)
This is a dual purpose flag. In FWFT mode, the Input Ready (IR) function
is selected. In IDT Standard mode, the Full Flag (
FF) functionisselected. For
both timing modes, when the Full/Input Ready flag is HIGH, a memory location
is free in the FIFO to receive new data. No memory locations are free when
the Full/Input Ready flag is LOW and attempted writes to the FIFO are ignored.
The Full/Input Ready flag of a FlFO is synchronized to the port clock that
writes data to its array (CLKA). For both FWFT and IDT Standard modes, each
timeawordiswrittentoaFIFO,itswritepointerisincremented. Thestatemachine
that controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory location is ready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizingclock. Therefore,anFull/InputReadyflagisLOWiflessthantwo
cycles of the Full/Input Ready flag synchronizing clock have elapsed since the
nextmemorywritelocationhasbeenread. ThesecondLOW-to-HIGHtransition
ontheFull/InputReadyflagsynchronizingclockafterthereadsetstheFull/Input
Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursattime
tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be
the first synchronization cycle (see Figures 13 and 14).
ALMOST-EMPTY FLAG (
AE)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads
data from its array (CLKB). The state machine that controls an Almost-Empty
flag monitors a write pointer and read pointer comparator that indicates when
theFIFOmemorystatusisalmost-empty,almost-empty+1,oralmost-empty+2.
TheAlmost-EmptystateisdefinedbythecontentsofregisterX. Theseregisters
are loaded with preset values during a FIFO reset, programmed from Port A,
or programmed serially (see Almost-Empty flag and Almost-Full flag offset
programmingsection). AnAlmost-EmptyflagisLOWwhenitsFIFOcontainsX
or less words and is HIGH when its FIFO contains (X+1) or more words. Note
thatadatawordpresentintheFIFOoutputregisterhasbeenreadfrommemory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock
are required after a FIFO write for its Almost-Empty flag to reflect the new level
offill. Therefore,theAlmost-EmptyflagofaFIFOcontaining(X+1)ormorewords
remainsLOWiftwocyclesofitssynchronizingclockhavenotelapsedsincethe
writethatfilledthememorytothe(X+1)level. AnAlmost-EmptyflagissetHIGH
bythesecondLOW-to-HIGHtransitionofitssynchronizingclockaftertheFIFO
writethatfillsmemorytothe(X+1)level. ALOW-to-HIGHtransitionofanAlmost-
Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycleifitoccurs
at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be the first synchro-
nization cycle. (See Figure 15).
ALMOST-FULL FLAG (
AF)
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
data to its array. The state machine that controls an Almost-Full flag monitors a
writepointerandreadpointercomparatorthatindicateswhentheFIFOmemory
statusisalmost-full,almost-full-1,oralmost-full-2. TheAlmost-Fullstateisdefined
by the contents of register Y. These registers are loaded with preset values
during a FlFO reset or, programmed from Port A, or programmed serially (see
Almost-EmptyflagandAlmost-Fullflagoffsetprogrammingsection). AnAlmost-
Full flag is LOW when the number of words in its FIFO is greater than or equal
to (256-Y), (512-Y), or (1,024-Y) for the IDT72V3623, IDT72V3633, or
IDT72V3643 respectively. An Almost-Full flag is HIGH when the number of
words in its FIFO is less than or equal to [256-(Y+1)], [512-(Y+1)], or [1,024-
(Y+1)] for the IDT72V3623, IDT72V3633, or IDT72V3643 respectively. Note
thatadatawordpresentintheFIFOoutputregisterhasbeenreadfrommemory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock
are required after a FIFO read for its Almost-Full flag to reflect the new level
of fill. Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-
(Y+1)]orlesswordsremainsLOWiftwocyclesofitssynchronizingclockhave
notelapsedsincethereadthatreducedthenumberofwordsinmemoryto[256/
512/1,024-(Y+1)]. AnAlmost-FullflagissetHIGHbythesecondLOW-to-HIGH
transitionofitssynchronizingclockaftertheFIFOreadthatreducesthenumber
of words in memory to [256/512/1,024-(Y+1)]. A LOW-to-HIGH transition of
an Almost-Full flag synchronizing clock begins the first synchronization cycle
if it occurs at time tSKEW2 or greater after the read that reduces the number of
words in memory to [256/512/1,024-(Y+1)]. Otherwise, the subsequent
synchronizing clock cycle may be the first synchronization cycle (see Figure
16).
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT72V3623/72V3633/72V3643
to pass command and control information between Port A and Port B without
putting it in queue. The Mailbox select (MBA, MBB) inputs choose between
a mail register and a FIFO for a port data transfer operation. The usable width
ofboththeMail1andMail2RegistersmatchestheselectedbussizeforPortB.
ALOW-to-HIGHtransitiononCLKAwritesdatatotheMail1Registerwhen
a Port A write is selected by
CSA, W/RA, and ENA with MBA HIGH. If the
selectedPortBbussizeis 36bits,theusablewidthoftheMail1Registeremploys
datalinesA0-A35. IftheselectedPortBbussizeis18bits,thentheusablewidth
of the Mail1 Register employs data lines A0-A17. (In this case, A18-A35 are
don’tcareinputs.) IftheselectedPortBbussizeis9bits,thentheusablewidth
oftheMail1RegisteremploysdatalinesA0-A8. (Inthiscase,A9-A35aredon’t
care inputs.)
A LOW-to-HIGH transition on CLKB writes B0-B35 data to the Mail2
Register when a Port B write is selected by
CSB, W/RB, and ENB with MBB
HIGH. If the selected Port B bus size is 36 bits, the usable width of the Mail2
employs data lines B0-B35. If the selected Port B bus size is 18 bits, then the
usable width of the Mail2 Register employs data lines B0-B17. (In this case,
B18-B35 are don’t care inputs.) If the selected Port B bus size is 9 bits, then
the usable width of the Mail2 Register employs data lines B0-B8. (In this case,
B9-B35 are don’t care inputs.)
Writingdatatoamailregistersetsitscorrespondingflag(
MBF1orMBF2)
LOW. AttemptedwritestoamailregisterareignoredwhilethemailflagisLOW.
When data outputs of a port are active, the data on the bus comes from
the FIFO output register when the port Mailbox select input is LOW and from
the mail register when the port Mailbox select input is HIGH.
TheMail1RegisterFlag(
MBF1)issetHIGHbyaLOW-to-HIGHtransition
on CLKB when a Port B read is selected by
CSB, W/RB, and ENB with MBB
HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35.
For an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. (In this
case, B18-B35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data
are placed on B0-B8. (In this case, B9-B35 are indeterminate.)
TheMail2RegisterFlag(
MBF2)issetHIGHbyaLOW-to-HIGHtransition
on CLKA when a Port A read is selected by
CSA, W/RA, and ENA with MBA
HIGH.
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| IDT72V3643L15PF | 功能描述:IC SYNCFIFO 1024X36 15NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3643L15PF8 | 功能描述:IC SYNCFIFO 1024X36 15NS 128TQFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3644L10PF | 功能描述:IC FIFO 2048X36 10NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3644L10PF8 | 功能描述:IC FIFO 2048X36 10NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
| IDT72V3644L15PF | 功能描述:IC FIFO 2048X36 15NS 128QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF |
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