IDT72V3623/72V3633/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING 256 x 36," />
參數(shù)資料
型號(hào)： IDT72V3643L10PF8
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 4/28頁(yè)
文件大?。?/td> 0K
描述： IC SYNCFIFO 1024X36 10NS 128TQFP
標(biāo)準(zhǔn)包裝： 1,000
系列： 72V
功能： 異步，同步
存儲(chǔ)容量： 36.8K（1K x 36）
數(shù)據(jù)速率： 100MHz
訪問(wèn)時(shí)間： 10ns
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 128-LQFP
供應(yīng)商設(shè)備封裝： 128-TQFP（14x20）
包裝： 帶卷 (TR)
其它名稱： 72V3643L10PF8
12
IDT72V3623/72V3633/72V3643 CMOS 3.3V SyncBiFIFOTM WITH BUS-MATCHING
256 x 36, 512 x 36, 1,024 x 36
COMMERCIAL TEMPERATURERANGE
the output register. When the Empty Flag is LOW, the previous data word is
present in the FIFO output register and attempted FIFO reads are ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the port clock
that reads data from its array (CLKB). For both the FWFT and IDT Standard
modes, the FIFO read pointer is incremented each time a new word is clocked
to its output register. The state machine that controls an Output Ready flag
monitors a write pointer and read pointer comparator that indicates when the
FIFO memory status is empty, empty+1, or empty+2.
In FWFT mode, from the time a word is written to a FIFO, it can be shifted
to the FIFO output register in a minimum of three cycles of the Output Ready
flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word
inmemoryisthenextdatatobesenttotheFlFOoutputregisterandthreecycles
oftheportClockthatreadsdatafromtheFIFOhavenotelapsedsincethetime
the word was written. The Output Ready flag of the FIFO remains LOW until
the third LOW-to-HIGH transition of the synchronizing clock occurs, simulta-
neously forcing the Output Ready flag HIGH and shifting the word to the FIFO
outputregister.
In IDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty
Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo
cyclesoftheEmptyFlagsynchronizingclock. Therefore,anEmptyFlagisLOW
if a word in memory is the next data to be sent to the FlFO output register and
two cycles of the port Clock that reads data from the FIFO have not elapsed
sincethetimethewordwaswritten. TheEmptyFlagoftheFIFOremainsLOW
until the second LOW-to-HIGH transition of the synchronizing clock occurs,
CSB
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
Port Functions
H
X
High-Impedance
None
L
X
Input
None
LL
H
L
↑
Input
None
LL
H
↑
Input
Mail2Write
L
H
L
X
Output
None
LH
H
L
↑
Output
FIFO read
L
H
L
H
X
Output
None
LH
H
↑
Output
Mail1 Read (Set
MBF1 HIGH)
TABLE 3 — PORT-B ENABLE FUNCTION TABLE
CSA
W/
RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
Port Functions
H
X
High-Impedance
None
L
H
L
X
Input
None
LH
H
L
↑
Input
FIFO Write
LH
H
↑
Input
Mail1Write
L
X
Output
None
LL
H
L
↑
Output
None
L
H
X
Output
None
LL
H
↑
Output
Mail2 Read (Set
MBF2 HIGH)
TABLE 2 — PORT-A ENABLE FUNCTION TABLE
TABLE 4 — FIFO FLAG OPERATION (IDT STANDARD AND FWFT MODES)
Synchronized
Number of Words in FIFO
(1,2)
to CLKB
to CLKA
IDT72V3623
(3)
IDT72V3633
(3)
IDT72V3643
(3)
EF/OR
AE
AF
FF/IR
000
L
H
1 to X
H
L
H
(X+1) to [256-(Y+1)]
(X+1) to [512-(Y+1)]
(X+1) to [1,024-(Y+1)]
H
(256-Y) to 255
(512-Y) to 511
(1,024-Y) to 1,023
H
L
H
256
512
1,024
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
read operation necessary), it is not included in the memory count.
3. X is the Almost-Empty offset used by
AE. Y is the Almost-Full offset used by AF. Both X and Y are selected during a FIFO reset or Port A programming.
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