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參數(shù)資料
| 型號： | IDT77155 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS |
| 中文描述： | 物理層（增距鏡TC - PMD）的用戶網(wǎng)絡(luò)接口的155Mbps的ATM網(wǎng)絡(luò)中的應(yīng)用 |
| 文件頁數(shù)： | 12/50頁 |
| 文件大?。?/td> | 307K |
| 代理商： | IDT77155 |
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8.03
12
IDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
verification while in SYNC state. The HEC verification state
machine is shown in Figure 2. The state machine is initialized
to “correction mode”. Cells with no HEC errors are passed to
the receive FIFO. Any single bit error detected in the incoming
cell headers are corrected and the cells are passed. It enters
into “detection mode” if any single bit or multi-bit errors in the
header are detected. In “detection mode”, all cells with single
or multi-bit errors are dropped. Only cells with no errors are
passed. When a cell with no HEC error is detected in “detec-
tion mode”, it enters back to “correction mode”. However, if
seven consecutive cells with errored HEC are received,
HUNT state is entered from the “detection mode”.
The ATM Descrambler descrambles the incoming 48 byte
cell payload only (header is not descrambled) by using poly-
nomial x
43
+ 1. The descrambling function may be disabled.
One 8-bit saturating HEC correctable error counter, one 8-
bit saturating HEC uncorrectable error counter, and a 19-bit
saturating receive cell counter are provided for ATM Cell
performance monitoring .
The HEC correctable error counter accumulates HEC
single bit errors in the header. The HEC uncorrectable error
counter accumulates HEC multiple bit errors in the header.
The receive cell counter accumulates the number of assigned
cells. All counters are active only in the SYNC state.
These three counter are to be read via microprocessor
interface at least once per second for performance monitor-
ing.
The received GFC bits are output in a serial stream via the
GFC Extraction output. GFC bits are extracted for every
received cell with the RCP output to indicate the position of the
most significant bit. The GFC output may be disabled via the
control register or no cell delineation.
The Receive FIFO has four ATM cells depth. It provides
FIFO management and the separation of STS-3c or STS-1
timing from ATM layer timing.
The FIFO management functions are to fill the receive four
cells FIFO and indicate when cells are ready to be read from
the receive FIFO and to detect FIFO overflow and underflow.
When overflow, the receive FIFO discards the incoming ATM
cells, a maskable interrupt and status register also active for
overflow condition. When underflow, the read is ignored.
When FIFO data is read out by RFCLK, the start of cell
(RSOC) is active. The cell available status (RCA) is provided
to indicate a cell is available in the receive FIFO.
CLOCK SYNTHESIS
The Clock Generator generates the 155.52 or 51.84 MHz
transmit clock by locking to a 1/8-frequency reference clock
i.e.,synthesized from a 19.44 MHz or 6.48 MHz reference
clock.
PARALLEL TO SERIAL
This block performs the parallel to serial conversion to
convert the outgoing byte serial data to bit serial data.
TRANSMIT SONET FRAMER
The Transmit SONET Framer provides framing pattern
(A1, A2) insertion, scrambling, pointer generation, SONET
section, line and path overhead insertion, and alarm signal
insertion.
The Framing pattern (A1, A2) and C1 are inserted into
outgoing STS-3c or STS-1 data stream. The framing bit error
may be insert for diagnostic.
The STS Scrambler scrambles the outgoing data except
framing bytes (A1, A2) and identity byte (C1) by the using
polynomial 1 + x
6
+ x
7
. Scrambling may be disabled via control
register. An “all-zero” pattern may be inserted via micropro-
cessor interface after scrambling for diagnostic information.
The outgoing section BIP-8 error detection code (B1) is
calculated over all bits of the complete STS-3c or STS-1 frame
after scrambling by bit interleaved parity calculation using
even parity. The calculated BIP-8 code is then inserted into
the B1 byte of the next outgoing frame before scrambling.
Corrupted BIP-8 code may be inserted via control register for
diagnostic information.
The Line AIS may be set for outgoing data stream by
inserting “all-one” pattern into line overhead and Synchro-
nous Payload Envelope (SPE) of STS-3c or STS-1 frame by
control register via microprocessor interface.
The Line Remote Defect Indication (RDI) may be set for
outgoing data stream by inserting “110” pattern in bits 6-8 of
K2 byte to generate Line RDI.
K1 and K2 byte may be inserted for outgoing data stream
for automatic switch protection (APS) use.
The outgoing line BIP-8 error detection code (B2) is calcu-
lated over all bits of the line overhead and Synchronous
Payload Envelope (SPE) of STS-3c or STS-1 frame before
scrambling by bit interleaved parity calculation using even
parity. The calculated BIP-8 code is then inserted to the B2
byte of the next outgoing frame before scrambling. Corrupted
BIP-8 code may be inserted via control register for diagnostic
information.
The Line FEBE can be inserted by accumulating detected
B2 BIP-8 errors from receive direction into FEBE code of the
third Z2 byte for transmit STS-3c frame.
The Pointer Generator generates the pointer (H1, H2) for
outgoing STS-3c or STS-1 data stream. The “ss” bits of
pointer is programmable for the SDH requirement. The loca-
tion of start of the Synchronous Payload Envelope (SPE) is
according to the value of generated pointer.
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| IDT77155L155PX | PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS |
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| IDT77301L12PF | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| IDT77301L12PFI | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| IDT77305 | UTOPIAFIFO 4 PORT MULTIPLEXER FIFO |
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| IDT77V011L155DA | 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
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