參數(shù)資料
型號: IDT77155
廠商: Integrated Device Technology, Inc.
英文描述: PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
中文描述: 物理層(增距鏡TC - PMD)的用戶網(wǎng)絡(luò)接口的155Mbps的ATM網(wǎng)絡(luò)中的應(yīng)用
文件頁數(shù): 27/50頁
文件大?。?/td> 307K
代理商: IDT77155
IIDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
8.03
27
RECEIVE PATH OVERHEAD STATUS REGISTER
ADDRESS 0X30
DEFAULT = 8’B00X0XX00
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
Symbol
LOP
PAIS
PRDI
Function
Reserved
Reserved
Receive loss of pointer (LOP) status indication.
Reserved
Receive path alarm indication (PAIS) status signal.
Receive path remote path indication status indication.
Reserved
Reserved
RECEIVE PATH OVERHEAD INTERRUPT REGISTER DEFAULT = 8’BX0X0XXXX
ADDRESS 0X31
Bit
Bit 7
Type
R
Symbol
C2Int
Function
C2 label bytes error interrupt. Asserted when the expected C2 value is
not received for 5 consecutive frames. The C2byte register (‘h37) stores
the most recently received C2 byte.
Reserved
Loss of pointer interrupt et when a change in LOP signal occurs. Cleared
when this register is read.
Reserved
Path alarm indication signal interrupt is asserted when a change in the
PAIS signal occurs. Cleared when this register is read.
Path RDI interrupt is asserted when a change in the path RDI signal
occurs. Cleared when this register is read.
Path BIP (B3) error interrupt is asserted when a path BIP (B3) error is
detected. Cleared when this register is read.
Path FEBE (bit 1-4 of G1) interrupt is asserted when a path FEBE is
detected. Cleared when this register is read.
Bit 6
Bit 5
R
LOPInt
Bit 4
Bit 3
R
PAISInt
Bit 2
R
PRDIInt
Bit 1
R
B3ErrInt
Bit 0
R
PFEBEInt
RECEIVE PATH OVERHEAD INTERRUPT ENABLE REGISTER
ADDRESS 0X33
DEFAULT = 8’B00000000
Bit
Bit 7
Type
R/W
Symbol
C2IEn
Function
C2 signal label bytes error interrupt enable If set to logic one, an interrupt
is generated if a C2 error is detected. C2 error occurs when unexpected
C2 bytes are received for 5 consecutive frames.
Reserved
Loss of pointer interrupt enable. If set to logic one, an interrupt is generated
if a LOP change is detected.
Reserved
Path alarm indication signal interrupt enable. If set to logic one, an
interrupt is generated if a PAIS change is detected.
Path RDI interrupt enable. If set to logic one, an interrupt is generated if a
path RDI change is detected.
Path BIP (B3) error interrupt enable. If set to logic one, an interrupt is
generated if a path BIP (B3) error is detected.
Path FEBE (bit 1-4 of G1) interrupt enable. If set to logic one, an interrupt
is generated if a path FEBE is detected.
Bit 6
Bit 5
R/W
LOPIEn
Bit 4
Bit3
R/W
PAISIEn
Bit 2
R/W
PRDIIEn
Bit 1
R/W
B3ErrIEn
Bit 0
R/W
PFEBEIEn
相關(guān)PDF資料
PDF描述
IDT77155L155PX PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
IDT77301 UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77301L12PF UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77301L12PFI UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77305 UTOPIAFIFO 4 PORT MULTIPLEXER FIFO
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