參數(shù)資料
型號： IDT77155
廠商： Integrated Device Technology, Inc.
英文描述： PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
中文描述： 物理層（增距鏡TC - PMD）的用戶網(wǎng)絡(luò)接口的155Mbps的ATM網(wǎng)絡(luò)中的應(yīng)用
文件頁數(shù)： 24/50頁
文件大?。?/td> 307K
代理商： IDT77155
8.03
24
IDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
RECEIVE LINE OVERHEAD STATUS REGISTER
ADDRESS 0X18
DEFAULT = 8’B00000000
Bit
Bit 7
Type
R/W
Symbol
B2Word
Function
Controls accumulation of B2 errors. If set to logic one, the B2 error counter
is incremented only once per frame for one or more errors received during
that frame. When disabled, the B2 error counter is incremented by the
received error count during that frame. Max B2 errors is 8 per frame for
STS-1 and 24 for STS-3c per frame.
Reserved
Reserved
Reserved
Reserved
Reserved
Receive line alarm signal status indication.
Receive line remote defect indication status indication.
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
—
—
R
R
—
—
—
—
—
LAIS
LRDI
RECEIVE LINE OVERHEAD INTERRUPT REGISTER
ADDRESS 0X19
DEFAULT = 8’B0000XXXX
Bit
Bit 7
Type
R/W
Symbol
LFEBEIEn
Function
Receive line FEBE (Z2) error interrupt enable. If set to logic one, an
interrupt is generated if a line FEBE is detected.
Receive line BIP (B2) error interrupt enable. If set to logic one, an
interrupt is generated if a line BIP (B2) error is detected.
Receive line alarm indication signal interrupt enable. If set to logic one, an
interrupt is generated if LAIS changes state.
Receive line RDI error interrupt enable. If set to logic one, an interrupt is
generated if line RDI signal changes state.
Receive line FEBE (Z2) error interrupt is asserted when a line FEBE
is detected. Cleared when this register is read.
Receive line BIP error interrupt is asserted when a B2 error is detected.
Cleared when this register is read.
Receive line alarm interrupt is asserted when a change in the line alarm
signal (LAIS) occurs. Cleared when this register is read.
Receive line RDI interrupt is asserted when a change in the line RDI
signal occurs. Cleared when this register is read.
Bit 6
R/W
B2ErrIEn
Bit 5
R/W
LAISIEn
Bit 4
R/W
LRDIIEn
Bit 3
R
LFEBEInt
Bit 2
R
B2ErrInt
Bit 1
R
LAISInt
Bit 0
R
LRDIInt
RECEIVE LINE OVERHEAD BIP ERROR COUNTER
DEFAULT = 20’HXXXXX
ADDRESS 0X1A
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Symbol
B2ErrCnt[7]
B2ErrCnt[6]
B2ErrCnt[5]
B2ErrCnt[4]
B2ErrCnt[3]
B2ErrCnt[2]
B2ErrCnt[1]
B2ErrCnt[0]
Function
B2 error counter bit
B2 error counter bit
B2 error counter bit
B2 error counter bit
B2 error counter bit
B2 error counter bit
B2 error counter bit
B2 error counter bit
相關(guān)PDF資料
PDF描述
IDT77155L155PX PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
IDT77301 UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77301L12PF UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77301L12PFI UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO
IDT77305 UTOPIAFIFO 4 PORT MULTIPLEXER FIFO
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT77155L155PX 制造商:INT_DEV_TECH 功能描述:
IDT77201L25PF 制造商:Integrated Device Technology Inc 功能描述:
IDT77211L155PQF 制造商:Integrated Device Technology Inc 功能描述:ATM/SONET SEGMENTATION AND REASSEMBLY CIRCUIT, 208 Pin, Plastic, QFP
IDT77V011L155DA 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
IDT77V011L155DA8 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標準包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2
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