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| 型號： | IDT82P5088BBG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 25/81頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/E1/J1 OCTAL 256PBGA |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 功能： | 線路接口單元（LIU） |
| 接口： | E1，J1，T1 |
| 電路數(shù)： | 8 |
| 電源電壓： | 1.8V, 3.3V |
| 功率（瓦特）： | 2.57W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（17x17） |
| 包裝： | 托盤 |
| 包括： | 集成式時鐘適配器 |
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IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
FUNCTIONAL DESCRIPTION
31
February 5, 2009
3.5
LOOPBACK
To facilitate testing and diagnosis, the IDT82P5088 provides four dif-
ferent loopback configurations: Analog Loopback, Digital Loopback,
Remote Loopback and Inband Loopback.
3.5.1
ANALOG LOOPBACK
WhentheALPbit(MAINT0,2BH...)issetto‘1’,thecorrespondingchan-
nel is configured in Analog Loopback mode. In this mode, the transmit sig-
nals are looped back to the Receiver Internal Termination in the receive
path then output from RCLKn, RDn, RDPn/RDNn. The all-ones pattern can
be generated during analog loopback. At the same time, the transmit sig-
nals arestill outputtoTTIPn/TRINGnin transmit direction.Figure-14shows
the process. The THZ bit (TCF1, 23H...) shall be set to ‘0’ in Analog Loop-
back mode.
3.5.2
DIGITAL LOOPBACK
WhentheDLPbit(MAINT0,2BH...)issetto‘1’,thecorrespondingchan-
nel is configured in Digital Loopback mode. In this mode, the transmit sig-
nals are looped back to the jitter attenuator (if enabled) and decoder in
receive path, then output from RCLKn, RDn, RDPn/RDNn. At the same
time, the transmit signals are still output to TTIPn/TRINGn in transmit direc-
tion. Figure-15 shows the process.
Both Analog Loopback mode and Digital Loopback mode allow the
sending of the internal patterns (All Ones, All Zeros, PRBS, etc.) which will
overwrite the transmit signals. In this case, either TCLKn or MCLK can be
used as the reference clock for internal patterns transmission.
3.5.3
REMOTE LOOPBACK
WhentheRLPbit(MAINT0,2BH...)issetto‘1’,thecorrespondingchan-
nel is configured in Remote Loopback mode. In this mode, the recovered
clock and data output from Clock and Data Recovery on the receive path
is looped back to the jitter attenuator (if enabled) and Waveform Shaper in
transmit path. Figure-16 shows the process.
Figure-14 Analog Loopback
Figure-15 Digital Loopback
One of the Eight Identical Channels
B8ZS/
HDB3/AMI
Encoder
Jitter
Attenuator
Line
Driver
Waveform
Shaper/LBO
B8ZS/
HDB3/AMI
Decoder
Jitter
Attenuator
Data
Slicer
Adaptive
Equalizer
LOS/AIS
Detector
Clock and
Data
Recovery
Transmitter
Internal
Termination
Receiver
Internal
Termination
TCLKn
TDNn
TDn/TDPn
RCLKn
CVn/RDNn
LOSn
RDn/RDPn
RRINGn
TTIPn
TRINGn
RTIPn
Analog
Loopback
One of the Eight Identical Channels
B8ZS/
HDB3/AMI
Encoder
Jitter
Attenuator
B8ZS/
HDB3/AMI
Decoder
Jitter
Attenuator
Data
Slicer
Adaptive
Equalizer
LOS/AIS
Detector
Clock and
Data
Recovery
Digital
Loopback
Receiver
Internal
Termination
TCLKn
TDNn
TDn/TDPn
RCLKn
CVn/RDNn
LOSn
RDn/RDPn
RRINGn
TTIPn
TRINGn
RTIPn
Line
Driver
Waveform
Shaper/LBO
Transmitter
Internal
Termination
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| IDT82P5088BBG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 OCTAL 256PBGA |
| IDT82V1054A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE |
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