參數(shù)資料
型號(hào)： IDT82P5088BBG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 42/81頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 OCTAL 256PBGA
標(biāo)準(zhǔn)包裝： 90
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 8
電源電壓： 1.8V, 3.3V
功率（瓦特）： 2.57W
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 托盤
包括： 集成式時(shí)鐘適配器
IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
PROGRAMMING INFORMATION
47
February 5, 2009
4.3.4
RECEIVE PATH CONTROL REGISTERS
Table-44 RJACF: Jitter Attenuator Configuration Register for Receive Path
(R/W, Address = X27H)
Symbol
Bit
Default
Description
-
7-6
00
Reserved
RJITT_TEST
5
0
This bit selects jitter measure mode
= 0: real time mode (update jitter measuring value each received clock cycle)
= 1: accumulation mode (measuring p-p value of jitter since last read)
RJA_LIMIT
4
1
Wide Jitter Attenuation bandwidth
= 0: normal mode
= 1: JA limit mode
RJA_E
3
00
Jitter Attenuator configuration
= 0: JA not used
= 1: JA enabled
RJA_DP[1:0]
2-1
00
Jitter Attenuator depth selection
= 00: 128 bits
= 01: 64 bits
= 10/11: 32 bits
RJA_BW
0
Jitter transfer function bandwidth selection
JABW
T1/J1
E1
0
5 Hz
6.77 Hz
1
1.26 Hz
0.87 Hz
Table-45 RCF0: Receiver Configuration Register 0 for Receive Path
(R/W, Address = X28H)
Symbol
Bit
Default
Description
-
7-5
000
Reserved
R_OFF
4
0
Receiver power down enable
= 0: Receiver power up
= 1: Receiver power down
RD_INV
3
0
Receive data invert
= 0: data on RDn or RDPn/RDNn is active high
= 1: data on RDn or RDPn/RDNn is active low
RCLK_SEL
2
0
Receive clock edge select (this bit is ignored in slicer mode)
= 0: data on RDn or RDPn/RDNn is updated on the rising edges of RCLKn
= 1: data on RDn or RDPn/RDNn is updated on the falling edges of RCLKn
R_MD[1:0]
1-0
00
Receiver path decoding selection
= 00: receive data is HDB3 (E1) / B8ZS (T1/J1) decoded and output on RDn with single rail NRZ format
= 01: receive data is AMI decoded and output on RDn with single rail NRZ format
= 10: decoder is bypassed, re-timed dual rail data with NRZ format output on RDPn/RDNn (dual rail mode with
clock recovery)
= 11: both CDR and decoder blocks are bypassed, slicer data with RZ format output on RDPn/RDNn (slicer mode)
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參數(shù)描述
IDT82P5088BBG8 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 OCTAL 256PBGA
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IDT82V1054APF 功能描述:IC PCM CODEC 4CH MPI 3.3V 64TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
IDT82V1054APF8 功能描述:IC PCM CODEC 4CH MPI 3.3V 64TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
IDT82V1054APFG 功能描述:IC PCM CODEC 4CH MPI 3.3V 64TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:16-SOIC 包裝:帶卷 (TR)
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