參數(shù)資料
型號(hào)： IDT82P5088BBG
廠商： IDT, Integrated Device Technology Inc
文件頁(yè)數(shù)： 31/81頁(yè)
文件大小： 0K
描述： IC LIU T1/E1/J1 OCTAL 256PBGA
標(biāo)準(zhǔn)包裝： 90
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 8
電源電壓： 1.8V, 3.3V
功率（瓦特）： 2.57W
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 托盤(pán)
包括： 集成式時(shí)鐘適配器
IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
FUNCTIONAL DESCRIPTION
37
February 5, 2009
3.9
MICROPROCESSOR INTERFACE
The microprocessor interface provides access to read and write the
registers in the device. The interface consists of Serial Peripheral Inter-
face (SPI) and parallel microprocessor interface.
3.9.1
SPI Mode
Pull the SPIEN pin to high, and the microprocessor interface will be
set in SPI mode.
In this mode, only the CS, SCLK, SDI and SDO pins are interfaced
with the microprocessor. A falling transition on CS pin indicates the start
of a read/write operation, and a rising transition indicates the end of the
operation. After the CS pin is set to low, two bytes include instruction
and address bytes on the SDI pin are input to the device on the rising
edge of the SCLK pin. First byte consists of one instruction bit at MSB
and three address bits at LSB, and the second byte is low 8 address
bits. If the MSB is ‘1’, it is read operation. If the MSB is ‘0’, it is write
operation. If the device is in read operation, the data read from the spec-
ified register is output on the SDO pin on the falling edge of the SCLK
(refer to Figure 21). If the device is in write operation, the data written to
the specified register is input on the SDI pin following the address byte
(refer to Figure 22).
Figure-21 Read Operation In SPI Mode
Figure-22 Write Operation In SPI Mode
3.9.2
Parallel Microprocessor Interface
Pull the SPIEN pin to low, the microprocessor interface will be set in
parallel mode. In this mode, the interface is compatible with the Motorola
and the Intel microprocessor, which is selected by the MPM pin. The
IDT82P5088 uses separate address bus and data bus. The mode selec-
tion and the interfaced pin are tabularized in Table 25.
CS
SCLK
SDI
SDO
10
1
2
3
4
5
6
7
8
9
11121314 1516 1718 1920 2122 23
A0
A7 A6 A5 A4 A3 A2 A1
Instruction
Register Address
High Impedance
D0
D7 D6 D5 D4 D3 D2 D1
Don't Care
A9
XX
X A11 A10
A8
0
CS
SCLK
SDI
SDO
10
0
1
2
3
4
5
6
7
8
9
11 12 13 14 15 16 17 18 19 20 21 22 23
A0
A7 A6 A5 A4 A3 A2 A1
Instruction
Data Byte
High Impedance
D0
D7 D6 D5 D4 D3 D2 D1
Register Address
A8
XX
X A11 A10 A9
Table-25 Parallel Microprocessor Interface
Pin MPM
Microprocessor Interface
Interfaced Pin
Low
Motorola
CS, DS, RW, A[10:0], D[7:0]
High
Intel
CS, RD, WR, A[10:0], D[7:0]
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