參數(shù)資料
型號(hào)： IDT82P5088BBG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 30/81頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 OCTAL 256PBGA
標(biāo)準(zhǔn)包裝： 90
功能： 線路接口單元（LIU）
接口： E1，J1，T1
電路數(shù)： 8
電源電壓： 1.8V, 3.3V
功率（瓦特）： 2.57W
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 256-BGA
供應(yīng)商設(shè)備封裝： 256-PBGA（17x17）
包裝： 托盤
包括： 集成式時(shí)鐘適配器
IDT82P5088
UNIVERSAL OCTAL T1/E1/J1 LIU WITH INTEGRATED CLOCK ADAPTER
FUNCTIONAL DESCRIPTION
36
February 5, 2009
3.8
CLOCK GENERATOR AND TCLK
3.8.1
CLOCK GENERATOR
Figure-19 Clock Generator
The OSCI pin is connected to an external Crystal Oscillator. In T1 mode
E1 Rate of Transmit System interface, this clock must keep the Crystal
Oscillator same with system transmit clock (TSCKn/MTSCK).
The OSCO pin outputs the inverted, buffered clock input from OSCI.
The clock frequency of OSCI is defined by CLK_SEL[2:0]. Refer to
The CLK_GEN_1.544 pin outputs the 1.544 MHz clock signal and the
CLK_GEN_2.048 outputs the 2.048 MHz clock signal.
The frequecy of the REFA_OUT/REFB_OUT pins is 2.048 MHz (E1)
or 1.544 MHz (T1/J1). When no LOS is detected, the REFA_OUT/
REFB_OUT pins output a recovered clock from the Clock and Data Recov-
ery function block of one of the eight links. The REFA_OUT link is selected
bytheRO1[2:0]bits(b2~0,T1/J1-007H/b2~0,E1-007H);The REFB_OUT
link is selected by the RO2[2:0] bits (b5~3, T1/J1-007H / b5~3, E1-007H).
When LOS is detected, the REFA_OUT/REFB_OUT pins output MCLK or
high level, as selected by the REFH_LOS bit (b0, T1/J1-03EH,... / b0, E1-
03EH,...). *
Note: MCLK is a clock derived from OSCI using an internal PLL, and the
frequency is 2.048 MHz (E1) or 1.544 MHz (T1/J1).
3.8.2
TRANSMIT CLOCK (TCLK)
The TCLKn is used to sample the transmit data on TDn/TDPn, TDNn.
The active edge of TCLKn can be selected by the TCLK_SEL bit (TCF0,
22H...). During Transmit All Ones, PRBS/QRSS patterns or Inband Loop-
back Code,either TCLKnor MCLK can beused as the referenceclock. This
is selected by the PATT_CLK bit (MAINT1, 2CH...).
But for Automatic Transmit All Ones and AIS, only MCLK is used as the
reference clock and the PATT_CLK bit is ignored. In Automatic Transmit
All Ones condition, the ATAO bit (MAINT1, 2CH) is set to ‘1’. In AIS condi-
tion, the RAISE bit (MAINT1, 2CH) is set to ‘1’.
If TCLKn has been missing for more than 70 MCLK cycles, TCLK_LOS
bit (STAT0, 36H...) will be set, and the corresponding TTIPn/TRINGn will
become high impedance if this channel is not used for remote loopback or
isnotusingMCLK totransmitinternal patterns (TAOS,AllZeros,PRBSand
in-band loopback code). When TCLKn is detected again, TCLK_LOS bit
(STAT0,36H...)willbecleared.ThereferencefrequencytodetectaTCLKn
loss is derived from MCLK.
Figure-20 TCLK Operation Flowchart
Table-24 Reference Clock Selection
CLK_SEL[2:0]
Input Clock Signal (MHz)
000
1 X 1.544
001
2 X 1.544
010
3 X 1.544
011
4 X 1.544
100
1 X 2.048
101
2 X 2.048
110
3 X 2.048
111
4 X 2.048
Clock Generator
CLK_GEN_1.544
Crystal
Oscillator
CLK_SEL[2:0]
OSCI
OSCO
CLK_GEN_2.048
REFA_OUT
REFB_OUT
normal operation mode
transmitter n enters high
impedance status and
generates transmit clock loss
interrupt if not masked
TCLKn status?
clocked
L/H
MCLK=H/L?
all transmitters high
impedance status
yes
clocked
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