Figure 20. Recommended LVDS Input Port Line Term" />
參數(shù)資料
型號: IDT82V3255TFG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 20/132頁
文件大?。?/td> 0K
描述: IC PLL WAN SMC STRATUM 3 64-TQFP
標準包裝: 1,250
類型: 時鐘/頻率發(fā)生器,多路復用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 3:3
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-TQFP(10x10)
包裝: 帶卷 (TR)
其它名稱: 82V3255TFG8
IDT82V3255
WAN PLL
Electrical Specifications
116
December 3, 2008
8.3.2.2
LVDS Input / Output Port
Figure 20. Recommended LVDS Input Port Line Termi-
nation
Figure 21. Recommended LVDS Output Port Line Ter-
mination
IN1_POS
IN1_NEG
IN2_POS
IN2_NEG
50
(transmission line)
100
2 kHz
to
667 MHz
100
2 kHz
to
667 MHz
50
(transmission line)
50
(transmission line)
50
(transmission line)
OUT1_POS
OUT1_NEG
100
2 kHz
to
667 MHz
50
(transmission line)
50
(transmission line)
Table 44: LVDS Input / Output Port Electrical Characteristics
Parameter
Description
Min
Typ
Max
Unit
Test Condition
VCM
Input Common-mode Voltage Range
0
1200
2400
mV
VDIFF
Input Peak Differential Voltage
100
900
mV
VIDTH
Input Differential Threshold
-100
100
mV
RTERM
External Differential Termination Impedance
95
100
105
VOH
Output Voltage High
1350
1475
mV
RLOAD = 100 ± 1%
VOL
Output Voltage Low
925
1100
mV
RLOAD = 100 ± 1%
VOD
Differential Output Voltage
250
400
mV
RLOAD = 100 ± 1%
VOS
Output Offset Voltage
1125
1275
mV
RLOAD = 100 ± 1%
RO
Differential Output Impedance
80
100
120
VCM = 1.0 V or 1.4 V
RO
RO Mismatch between A and B
20
%
VCM = 1.0 V or 1.4 V
VOD
Change in VOD between Logic 0 and Logic 1
25
mV
RLOAD = 100 ± 1%
VOS
Change in VOS between Logic 0 and Logic 1
25
mV
RLOAD = 100 ± 1%
ISA, ISB
Output Current
24
mA
Driver shorted to GND
ISAB
Output Current
12
mA
Driver shorted together
tRISE
Output Rise time (20% to 80%)
200
300
pS
RLOAD = 100 ± 1%
tFALL
Output Fall time (20% to 80%)
200
300
pS
RLOAD = 100 ± 1%
tSKEW
Output Differential Skew
50
pS
RLOAD = 100 ± 1%
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