- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9574 > IDT82V3255TFG8 (IDT, Integrated Device Technology Inc)IC PLL WAN SMC STRATUM 3 64-TQFP PDF資料下載
參數(shù)資料
| 型號： | IDT82V3255TFG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 44/132頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL WAN SMC STRATUM 3 64-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,250 |
| 類型： | 時鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，PECL |
| 輸出： | CMOS，LVDS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:3 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 82V3255TFG8 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當(dāng)前第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁
IDT82V3255
WAN PLL
Functional Description
19
December 3, 2008
3.4
INPUT CLOCK PRE-DIVIDER
Each input clock is assigned an internal Pre-Divider. The Pre-Divider
is used to divide the clock frequency down to the DPLL required fre-
quency, which is no more than 38.88 MHz. For each input clock, the
DPLL required frequency is set by the corresponding IN_FREQ[3:0] bits.
If the input clock is of 2 kHz, 4 kHz or 8 kHz, the Pre-Divider is
bypassed automatically and the corresponding IN_FREQ[3:0] bits
should be set to match the input frequency; the input clock can be
inverted, as determined by the IN_2K_4K_8K_INV bit.
Each Pre-Divider consists of a HF (High Frequency) Divider (only
available for IN1_DIFF and IN2_DIFF), a DivN Divider and a Lock 8k
Divider, as shown in Figure 3.
The HF Divider, which is only available for IN1_DIFF and IN2_DIFF,
should be used when the input clock is higher than (
>) 155.52 MHz. The
input clock can be divided by 4, 5 or can bypass the HF Divider, as
determined by the IN1_DIFF_DIV[1:0]/IN2_DIFF_DIV[1:0] bits corre-
spondingly.
Either the DivN Divider or the Lock 8k Divider can be used or both
can be bypassed, as determined by the DIRECT_DIV bit and the
LOCK_8K bit.
When the DivN Divider is used, the division factor setting should
observe the following order:
1. Select an input clock by the PRE_DIV_CH_VALUE[3:0] bits;
2. Write the lower eight bits of the division factor to the
PRE_DIVN_VALUE[7:0] bits;
3. Write the higher eight bits of the division factor to the
PRE_DIVN_VALUE[14:8] bits.
Once the division factor is set for the input clock selected by the
PRE_DIV_CH_VALUE[3:0] bits, it is valid until a different division factor
is set for the same input clock. The division factor is calculated as fol-
lows:
Division Factor = (the frequency of the clock input to the DivN
Divider ÷ the frequency of the DPLL required clock set by the
IN_FREQ[3:0] bits) - 1
The DivN Divider can only divide the input clock whose frequency is
lower than (
<) 155.52 MHz.
When the Lock 8k Divider is used, the input clock is divided down to
8 kHz automatically.
The Pre-Divider configuration and the division factor setting depend
on the input clock on one of the clock input pin and the DPLL required
clock. Here is an example:
The input clock on the IN2_DIFF pin is 622.08 MHz; the DPLL
required clock is 6.48 MHz by programming the IN_FREQ[3:0] bits of
register IN2_DIFF to ‘0010’. Do the following step by step to divide the
input clock:
1. Use the HF Divider to divide the clock down to 155.52 MHz:
622.08 ÷ 155.52 = 4, so set the IN2_DIFF_DIV[1:0] bits to ‘01’;
2. Use the DivN Divider to divide the clock down to 6.48 MHz:
Set the PRE_DIV_CH_VALUE[3:0] bits to ‘0110’;
Set the DIRECT_DIV bit in Register IN2_DIFF_CNFG to ‘1’ and
the LOCK_8K bit in Register IN2_DIFF_CNFG to ‘0’;
155.52 ÷ 6.48 = 24; 24 - 1 = 23, so set the
PRE_DIVN_VALUE[14:0] bits to ‘10111’.
Figure 3. Pre-Divider for An Input Clock
Table 4: Related Bit / Register in Chapter 3.4
Bit
Register
Address (Hex)
IN1_DIFF_DIV[1:0]
IN1_DIFF_IN2_DIFF_HF_DIV_CNFG
18
IN2_DIFF_DIV[1:0]
IN_FREQ[3:0]
IN1_CMOS_CNFG, IN2_CMOS_CNFG, IN1_DIFF_CNFG, IN2_DIFF_CNFG,
IN3_CNFG
16, 17, 19, 1A, 1D
DIRECT_DIV
LOCK_8K
IN_2K_4K_8K_INV
FR_MFR_SYNC_CNFG
74
PRE_DIV_CH_VALUE[3:0]
PRE_DIV_CH_CNFG
23
PRE_DIVN_VALUE[14:0]
PRE_DIVN[14:8]_CNFG, PRE_DIVN[7:0]_CNFG
25, 24
input clock
DivN Divider
Lock 8k Divider
HF Divider
(for IN1_DIFF &
IN2_DIFF only)
Pre-Divider
IN1_DIFF_DIV[1:0] bits / IN2_DIFF_DIV[1:0] bits
DIRECT_DIV bit
LOCK_8K bit
DPLL required clock
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CS3102A-14S-54S | CONN RCPT 6POS BOX MNT W/SCKT |
| MS3450L18-9SY | CONN RCPT 7POS WALL MNT W/SCKT |
| MS27497E24B1SA | CONN RCPT 128POS WALL MNT W/SCKT |
| MS3128E16-26S | CONN RCPT 26POS WALL MNT W/SCKT |
| MS3450L18-9SX | CONN RCPT 7POS WALL MNT W/SCKT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3255TFGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280_08 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280APFG | 功能描述:IC PLL WAN SE STRATUM 2 100TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| IDT82V3280APFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 2 100TQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。