參數(shù)資料
型號(hào)： IDT82V3280
廠商： Integrated Device Technology, Inc.
英文描述： WAN PLL
中文描述： 廣域網(wǎng)鎖相環(huán)
文件頁數(shù)： 10/167頁
文件大小： 1039K
代理商： IDT82V3280
IDT82V3280
WAN PLL
Description
10
June 19, 2006
DESCRIPTION
The IDT82V3280 is an integrated, single-chip solution for the Syn-
chronous Equipment Timing Source for Stratum 2, 3E, 3, SMC, 4E and 4
clocks in SONET / SDH equipments, DWDM and Wireless base station,
such as GSM, 3G, DSL concentrator, Router and Access Network appli-
cations.
The device supports three types of input clock sources: recovered
clock from STM-N or OC-n, PDH network synchronization timing and
external synchronization reference timing.
Based on ITU-T G.783 and Telcordia GR-253-CORE, the device con-
sists of T0 and T4 paths. The T0 path is a high quality and highly config-
urable path to provide system clock for node timing synchronization
within a SONET / SDH network. The T4 path is simpler and less config-
urable for equipment synchronization. The T4 path locks independently
from the T0 path or locks to the T0 path.
An input clock is automatically or manually selected for T0 and T4
each for DPLL locking. Both the T0 and T4 paths support three primary
operating modes: Free-Run, Locked and Holdover. In Free-Run mode,
the DPLL refers to the master clock. In Locked mode, the DPLL locks to
the selected input clock. In Holdover mode, the DPLL resorts to the fre-
quency data acquired in Locked mode. Whatever the operating mode is,
the DPLL gives a stable performance without being affected by operat-
ing conditions or silicon process variations.
If the DPLL outputs are processed by T0/T4 APLL, the outputs of the
device will be in a better jitter/wander performance.
The device provides programmable DPLL bandwidths: 0.5 mHz to
560 Hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. Different
settings cover all SONET / SDH clock synchronization requirements.
A high stable input is required for the master clock in different appli-
cations. The master clock is used as a reference clock for all the internal
circuits in the device. It can be calibrated within ±741 ppm.
All the read/write registers are accessed through a microprocessor
interface. The device supports five microprocessor interface modes:
EPROM, Multiplexed, Intel, Motorola and Serial.
In general, the device can be used in Master/Slave application. In
this application, two devices should be used together to enable system
protection against single chip failure. See
Chapter 4 Typical Application
for details.
相關(guān)PDF資料
PDF描述
IDT82V3280DQ WAN PLL
IDT82V3280DQG WAN PLL
IDT82V3280PF WAN PLL
IDT82V3280PFG WAN PLL
IDT82V3288 WAN PLL
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT82V3280_08 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3280APFG 功能描述:IC PLL WAN SE STRATUM 2 100TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3280APFG8 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 2 100TQFP
IDT82V3280DQ 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3280DQG 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*