參數(shù)資料
型號： IDT82V3280
廠商： Integrated Device Technology, Inc.
英文描述： WAN PLL
中文描述： 廣域網(wǎng)鎖相環(huán)
文件頁數(shù)： 30/167頁
文件大?。?/td> 1039K
代理商： IDT82V3280
IDT82V3280
WAN PLL
Functional Description
30
June 19, 2006
3.8.2.2
Non-Revertive Switch (T0 only)
In Non-Revertive switch, the T0 selected input clock is not switched
when another qualified input clock with a higher priority than the current
selected input clock is available. In this case, the selected input clock is
switched and a qualified input clock with the highest priority is selected
only when the T0 selected input clock is disqualified. If more than one
qualified input clock is available and has the same priority, the input
clock with the smallest ‘n’ is selected.
3.8.3
SELECTED / QUALIFIED INPUT CLOCKS INDICATION
The
selected
input
clock
is
indicated
by
the
CURRENTLY_SELECTED_INPUT[3:0] bits. Note if the T4 selected
input clock is a T0 DPLL output, it can not be indicated by these bits.
The qualified input clocks with the three highest priorities are indi-
cated by HIGHEST_PRIORITY_VALIDATED[3:0] bits, the SECOND_
PRIORITY_VALIDATED[3:0]
bits
_VALIDATED[3:0] bits respectively. If more than one input clock INn has
the same priority, the input clock with the smallest ‘n’ is indicated by the
HIGHEST_PRIORITY_VALIDATED[3:0] bits.
and
the
THIRD_PRIORITY
When the device is configured in Automatic selection and Revertive
switch
is
enabled,
the
input
CURRENTLY_SELECTED_INPUT[3:0] bits is the same as the one indi-
cated by the HIGHEST_PRIORITY_VALIDATED[3:0] bits; otherwise,
they are not the same.
clock
indicated
by
the
When all the input clocks for T4 path changes to be unqualified, the
INPUT_TO_T4
1
bit will be set. If the INPUT_TO_T4
2
bit is ‘1’, an inter-
rupt will be generated.
Table 14: Related Bit / Register in Chapter 3.8
Bit
Register
Address (Hex)
T0_FOR_T4
INn
1
(14
≥
n
≥
1)
INn
2
(14
≥
n
≥
1)
INn
3
(14
≥
n
≥
1)
AMI1_LOS
AMI2_LOS
T4_INPUT_SEL_CNFG
INPUT_VALID1_STS, INPUT_VALID2_STS
51
4A, 4B
INTERRUPTS1_STS, INTERRUPTS2_STS
0D, 0E
INTERRUPTS1_ENABLE_CNFG, INTERRUPTS2_ENABLE_CNFG
10, 11
INTERRUPTS3_STS
0F
INn_NO_ACTIVITY_ALARM
(14
≥
n
≥
1)
INn_FREQ_HARD_ALARM
(14
≥
n
≥
1)
INn_PH_LOCK_ALARM (14
≥
n
≥
1)
IN_NOISE_WINDOW
ULTR_FAST_SW
LOS_FLAG_TO_TDO
T0_MAIN_REF_FAILED
1
T0_MAIN_REF_FAILED
2
INPUT_TO_T4
1
INPUT_TO_T4
2
REVERTIVE_MODE
INn_SEL_PRIORITY[3:0] (14
≥
n
≥
1)
INn_VALID (14
≥
n
≥
1)
CURRENTLY_SELECTED_INPUT[3:0]
HIGHEST_PRIORITY_VALIDATED[3:0]
SECOND_PRIORITY_VALIDATED[3:0]
THIRD_PRIORITY_VALIDATED[3:0]
T4_T0_SEL
Note: *
The setting in the 26 ~ 2C, 4E and 4F registers is either for T0 path or for T4 path, as determined by the T4_T0_SEL bit.
IN1_IN2_STS ~ IN13_IN14_STS
43 ~ 49
PHASE_MON_PBO_CNFG
78
MON_SW_PBO_CNFG
0B
INTERRUPTS2_STS
0E
INTERRUPTS2_ENABLE_CNFG
11
INTERRUPTS3_STS
0F
INTERRUPTS3_ENABLE_CNFG
INPUT_MODE_CNFG
12
09
IN1_IN2_SEL_PRIORITY_CNFG ~ IN13_IN14_SEL_PRIORITY_CNFG
REMOTE_INPUT_VALID1_CNFG, REMOTE_INPUT_VALID2_CNFG
26 ~ 2C *
4C, 4D
PRIORITY_TABLE1_STS
4E *
PRIORITY_TABLE2_STS
4F *
T4_T0_REG_SEL_CNFG
07
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PDF描述
IDT82V3280DQ WAN PLL
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相關代理商/技術參數(shù)
參數(shù)描述
IDT82V3280_08 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3280APFG 功能描述:IC PLL WAN SE STRATUM 2 100TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
IDT82V3280APFG8 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 2 100TQFP
IDT82V3280DQ 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL
IDT82V3280DQG 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT
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