20
AT90PWM216/316 [DATASHEET]
7710H–AVR–07/2013
5.3.4
The EEPROM Control Register – EECR
Bits 7..6 – Reserved Bits
These bits are reserved bits in the AT90PWM216/316 and will always read as zero.
Bits 5..4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing
EEWE. It is possible to program data in one atomic operation (erase the old value and program the new value) or
to split the Erase and Write operations in two different operations. The Programming times for the different modes
are shown in
Table 5-1. While EEWE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will
be reset to 0b00 unless the EEPROM is busy programming.
Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero dis-
ables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared. The
interrupt will not be generated during EEPROM write or SPM.
Bit 2 – EEMWE: EEPROM Master Write Enable
The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is
set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is
zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware clears the bit
to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.
Bit 1 – EEWE: EEPROM Write Enable
The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are cor-
rectly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be
written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following pro-
cedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):
1.
Wait until EEWE becomes zero.
2.
Wait until SPMEN (Store Program Memory Enable) in SPMCSR (Store Program Memory Control and Sta-
tus Register) becomes zero.
3.
Write new EEPROM address to EEAR (optional).
4.
Write new EEPROM data to EEDR (optional).
5.
Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.
6.
Within four clock cycles after setting EEMWE, write a logical one to EEWE.
Bit
765
43
2
1
0
–
EEPM1
EEPM0
EERIE
EEMWE
EEWE
EERE
EECR
Read/Write
R
R/W
Initial Value
0
X
0
X
0
Table 5-1.
EEPROM Mode Bits
EEPM1
EEPM0
Programming
Time
Operation
0
3.4 ms
Erase and Write in one operation (Atomic Operation)
0
1
1.8 ms
Erase Only
1
0
1.8 ms
Write Only
1
–
Reserved for future use