157
AT90PWM216/316 [DATASHEET]
7710H–AVR–07/2013
Clear this bit to select the slow clock input (CLKPS).
Bit 0 – POME2: PSC 2 Output Matrix Enable (PSC2 only)
When Output Matrix is used, the PSC n Output Polarity POPn has no action on the outputs.
15.25.11 PSC 0 Control Register – PCTL0
Bit 7:6 – PPRE01:0 : PSC 0 Prescaler Select
This two bits select the PSC input clock division factor. All generated waveform will be modified by this factor.
Bit 5 – PBFM0 : Balance Flank Width Modulation
When this bit is clear, Flank Width Modulation operates on On-Time 1 only.
When this bit is set, Flank Width Modulation operates on On-Time 0 and On-Time 1.
Bit 4 – PAOC0B : PSC 0 Asynchronous Output Control B
When this bit is set, Fault input selected to block B can act directly to PSCOUT01 output. See
See “PSC Input Con- Bit 3 – PAOC0A : PSC 0 Asynchronous Output Control A
When this bit is set, Fault input selected to block A can act directly to PSCOUT00 output. See
See “PSC Input Con- Bit 2 – PARUN0 : PSC 0 Autorun
When this bit is set, the PSC 0 starts with PSC2. That means that PSC 0 starts :
when PRUN2 bit in PCTL2 is set,
or when PARUN2 bit in PCTL2 is set and PRUN1 bit in PCTL1 register is set.
Thanks to this bit, 2 or 3 PSCs can be synchronized (motor control for example)
Bit 1 – PCCYC0 : PSC 0 Complete Cycle
When this bit is set, the PSC 0 completes the entire waveform cycle before halt operation requested by clearing
PRUN0. This bit is not relevant in slave mode (PARUN0 = 1).
Bit 0 – PRUN0 : PSC 0 Run
Writing this bit to one starts the PSC 0.
Bit
7
654
3
2
1
0
PPRE01
PPRE00
PBFM0
PAOC0B
PAOC0A
PARUN0
PCCYC0
PRUN0
PCTL0
Read/Write
R/W
Initial Value
0
Table 15-14. PSC 0 Prescaler Selection
PPRE01
PPRE00
Description
0
No divider on PSC input clock
0
1
Divide the PSC input clock by 4
1
0
Divide the PSC input clock by 32
1
Divide the PSC clock by 256