155
AT90PWM216/316 [DATASHEET]
7710H–AVR–07/2013
When this bit is set, I/O pin relating to PSCOUT22 is connected to PSC2 waveform generator A or B output
(according to POS22 setting) and is set and clear according to PSC2 operation.
Bit 0 – POENnA: PSC n OUT Part A Output Enable
When this bit is clear, I/O pin affected to PSCOUTn0 acts as a standard port.
When this bit is set, I/O pin affected to PSCOUTn0 is connected to the PSC waveform generator A output and is
set and clear according to the PSC operation.
15.25.4
Output Compare SA Register – OCRnSAH and OCRnSAL
15.25.5
Output Compare RA Register – OCRnRAH and OCRnRAL
15.25.6
Output Compare SB Register – OCRnSBH and OCRnSBL
15.25.7
Output Compare RB Register – OCRnRBH and OCRnRBL
Note : n = 0 to 2 according to PSC number.
The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously compared with the
PSC counter value. A match can be used to generate an Output Compare interrupt, or to generate a waveform out-
put on the associated pin.
The Output Compare Registers RB contains also a 4-bit value that is used for the flank width modulation.
The Output Compare Registers are 16bit and 12-bit in size. To ensure that both the high and low bytes are written
simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary high byte
register (TEMP). This temporary register is shared by all the other 16-bit registers.
15.25.8
PSC 0 Configuration Register – PCNF0
Bit
76543210
––––
OCRnSA[11:8]
OCRnSAH
OCRnSA[7:0]
OCRnSAL
Read/Write
R/W
Initial Value
00000000
Bit
76543210
––––
OCRnRA[11:8]
OCRnRAH
OCRnRA[7:0]
OCRnRAL
Read/Write
WWWWWWWW
Initial Value
00000000
Bit
76543210
––––
OCRnSB[11:8]
OCRnSBH
OCRnSB[7:0]
OCRnSBL
Read/Write
WWWWWWWW
Initial Value
00000000
Bit
76543210
OCRnRB[15:12]
OCRnRB[11:8]
OCRnRBH
OCRnRB[7:0]
OCRnRBL
Read/Write
R/W
Initial Value
00000000
Bit
7
654
3
2
1
0
PFIFTY0
PALOCK0
PLOCK0
PMODE01
PMODE00
POP0
PCLKSEL0
-
PCNF0
Read/Write
R/W
Initial Value
0