29
AT90PWM216/316 [DATASHEET]
7710H–AVR–07/2013
Notes:
1. The device is shipped with this option selected.
2. If 8 MHz frequency exceeds the specification of the device (depends on V
CC), the CKDIV8 Fuse can be pro-
grammed in order to divide the internal frequency by 8.
When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in
Table 6-6 on pageNote:
1. If the RSTDISBL fuse is programmed, this start-up time will be increased to
14CK + 4.1 ms to ensure programming mode can be entered.
2. The device is shipped with this option selected.
6.5.1
Oscillator Calibration Register – OSCCAL
Bits 7..0 – CAL7..0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process varia-
tions from the oscillator frequency. The factory-calibrated value is automatically written to this register during chip
reset, giving an oscillator frequency of 8.0 MHz at 25°C. The application software can write this register to change
the oscillator frequency. The oscillator can be calibrated to any frequency in the range 7.3 - 8.1 MHz within ±1%
accuracy. Calibration outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected
accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Otherwise, the EEPROM
or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency
range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other
words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.
The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest fre-
quency in that range, and a setting of 0x7F gives the highest frequency in the range. Incrementing CAL6..0 by 1
will give a frequency increment of less than 2% in the frequency range 7.3 - 8.1 MHz.
6.6
PLL
To generate high frequency and accurate PWM waveforms, the ‘PSC’s need high frequency clock input. This clock
is generated by a PLL. To keep all PWM accuracy, the frequency factor of PLL must be configurable by software.
With a system clock of 8 MHz, the PLL output is 32Mhz or 64Mhz.
Table 6-6.
Start-up times for the internal calibrated RC Oscillator clock selection
Power Conditions
Start-up Time from Power-
down and Power-save
Additional Delay from
Reset (VCC = 5.0V)
SUT1..0
BOD enabled
6 CK
00
Fast rising power
6 CK
14CK + 4.1 ms
01
Slowly rising power
6 CK
10
Reserved
11
Bit
76543210
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
OSCCAL
Read/Write
R/W
Initial Value
Device Specific Calibration Value