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參數(shù)資料
| 型號(hào)： | Intel386 EX |
| 廠商： | Intel Corp. |
| 英文描述： | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| 中文描述： | 高度集成，32位，全靜態(tài)嵌入式Micropocessor（32位高集成完全靜態(tài)嵌入式微處理器） |
| 文件頁數(shù)： | 15/48頁 |
| 文件大?。?/td> | 515K |
| 代理商： | INTEL386 EX |
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Special Environment
Intel386 EX Embedded Processor
PRELIMINARY
11
4.0
FUNCTIONAL DESCRIPTION
The Special Environment Intel386 EX embedded
processor is a fully static, 32-bit processor optimized
for harsh environment embedded applications. It
features low power and low voltage capabilities,
integration of many commonly used peripherals, and
a 32-bit programming architecture compatible with
the large software base of Intel386 processors. The
following sections provide an overview of the
integrated peripherals.
4.1
Clock Generation and Power
Management Unit
The clock generation circuit includes a divide-by-two
counter, a programmable divider for generating a
prescaled clock (PSCLK), a divide-by-two counter
for generating baud-rate clock inputs, and Reset
circuitry. The CLK2 input provides the fundamental
timing for the chip. It is divided by two internally to
generate a 50% duty cycle Phase1 (PH1) and Phase
2 (PH2) for the core and integrated peripherals. For
power management, separate clocks are routed to
the core (PH1C/PH2C) and the peripheral modules
(PH1P/PH2P).
Two Power Management modes are provided for
flexible power-saving options. During Idle mode, the
clocks to the CPU core are frozen in a known state
(PH1C low and PH2C high), while the clocks to the
peripherals continue to toggle. In Powerdown mode,
the clocks to both core and peripherals are frozen in
a known state (PH1C low and PH2C high). The Bus
Interface Unit will not honor any DMA, DRAM
refresh, or HOLD requests in Powerdown mode
because the clocks to the entire device are frozen.
4.2
Chip-select Unit
The Chip-select Unit (CSU) decodes bus cycle
address and status information and enables the
appropriate chip-selects. The individual chip-selects
become valid in the same bus state as the address
and become inactive when either a new address is
selected or the current bus cycle is complete.
The CSU is divided into eight separate chip-select
regions, each of which can enable one of the eight
chip-select pins. Each chip-select region can be
mapped into memory or I/O space. A memory-
mapped chip-select region can start on any 2
(n+1)
Kbyte address location (where n = 0–15, depending
upon the mask register). An I/O-mapped chip-select
region can start on any 2
(n+1)
byte address location
(where n = 0–15, depending upon the mask
register).
The size of the region is also dependent
upon the mask used.
4.3
Interrupt Control Unit
The Interrupt Control Unit (ICU) contains two
82C59A modules connected in a cascade mode.
The 82C59A modules make up the heart of the ICU.
These modules are similar to the industry-standard
82C59A architecture.
The Interrupt Control Unit directly supports up to
eight external (INT7:0) and up to eight internal
interrupt request signals. Pending interrupt requests
are posted in the Interrupt Request Register, which
contains one bit for each interrupt request signal.
When an interrupt request is asserted, the corre-
sponding Interrupt Request Register bit is set. The
82C59A module can be programmed to recognize
either an active-high level or a positive transition on
the interrupt request lines. An internal Priority
Resolver decides which pending interrupt request (if
more than one exists) is the highest priority, based
on the programmed operating mode. The Priority
Resolver controls the single interrupt request line to
the CPU. The Priority Resolver’s default priority
scheme places the master interrupt controller’s IR0
as the highest priority and the master’s IR7 as the
lowest. The priority can be modified through
software.
Besides the eight interrupt request inputs available,
additional interrupts can be supported by cascaded
external 82C59A modules. Up to four external
82C59A units can be cascaded to the master
through connections to the INT3:0 pins. In this
configuration, the interrupt acknowledge (INTA#)
signal can be decoded externally using the ADS#,
D/C#, W/R#, and M/IO# signals.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
| Intel387 sx | SX Math Coprocessor(32位數(shù)學(xué)協(xié)處理器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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