
Contents
iii
SPECIAL ENVIRONMENT Intel386 EX
EMBEDDED MICROPROCESSOR
1.0 INTRODUCTION ........................................................................................................................................1
2.0 PIN ASSIGNMENT ....................................................................................................................................2
3.0 PIN DESCRIPTION ....................................................................................................................................7
4.0 FUNCTIONAL DESCRIPTION ................................................................................................................11
4.1 Clock Generation and Power Management Unit ..............................................................................11
4.2 Chip-select Unit ................................................................................................................................11
4.3 Interrupt Control Unit ........................................................................................................................11
4.4 Timer Control Unit ............................................................................................................................12
4.5 Watchdog Timer Unit ........................................................................................................................12
4.6 Asynchronous Serial I/O Unit ...........................................................................................................12
4.7 Synchronous Serial I/O Unit .............................................................................................................12
4.8 Parallel I/O Unit ................................................................................................................................12
4.9 DMA and Bus Arbiter Unit ................................................................................................................12
4.10 Refresh Control Unit .......................................................................................................................13
4.11 JTAG Test-logic Unit ......................................................................................................................13
5.0 DESIGN CONSIDERATIONS ..................................................................................................................13
5.1 Instruction Set ...................................................................................................................................13
5.2 Component and Revision Identifiers .................................................................................................14
5.3 Package Thermal Specifications ......................................................................................................14
6.0 DC SPECIFICATIONS .............................................................................................................................17
6.1 Maximum Ratings .............................................................................................................................17
6.2 Operating Conditions ........................................................................................................................17
7.0 AC SPECIFICATIONS .............................................................................................................................18
8.0 BUS CYCLE WAVEFORMS ....................................................................................................................32
9.0 INTERFACE TO Intel387
TM
SX MATH COPROCESSOR ......................................................................42
9.1 System Configuration .......................................................................................................................42
10.0 REVISION HISTORY .............................................................................................................................43
FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Intel386 EX Embedded Processor Block Diagram .................................................................1
168-Lead Pin Grid Array Pinout (Bottom View — Pin Side) ......................................................2
168-Lead Pin Grid Array Pinout (Top View — Component Side) ..............................................3
164-Pin CQFP Pin Assignment .................................................................................................5
Drive Levels and Measurement Points for AC Specifications ..................................................19
AC Test Loads .........................................................................................................................25
CLK2 Waveform ......................................................................................................................25
CLK2 Signal and Internal Processor Clock ..............................................................................26
AC Timing Waveforms — Input Setup and Hold Timing ..........................................................27
AC Timing Waveforms — Output Valid Delay Timing .............................................................28
AC Timing Waveforms — Output Float Delay and HLDA Valid Delay Timing .........................29