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參數(shù)資料
| 型號： | Intel386 EX |
| 廠商： | Intel Corp. |
| 英文描述： | Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器) |
| 中文描述： | 高度集成，32位，全靜態(tài)嵌入式Micropocessor（32位高集成完全靜態(tài)嵌入式微處理器） |
| 文件頁數(shù)： | 39/48頁 |
| 文件大小： | 515K |
| 代理商： | INTEL386 EX |
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Special Environment
Intel386 EX Embedded Processor
PRELIMINARY
35
Figure 19. Pipelined Local Bus Read and Write Cycles (With Wait States)
A2477-02
DATA
CLK2
W/R#
NA#
T1P
T2P
T2P
T1P
T2
T2P
T1P
T2i
T2P
T1P
Cycle1
Pipelined
(Write)
Cycle2
Pipelined
(Read)
Cycle3
Pipelined
(Write)
Cycle4
Pipelined
(Read)
PH2
ADS# is asserted
as soon as the CPU
has another bus
cycle to perform,
which is not always
immediately after
NA# is asserted.
As long as the CPU
enters the T2P state
during Cycle3, address
pipelining is maintained
in Cycle 4.
Note ADS# is
asserted in
every T2P state.
Out 1
Out
NA# could have been asserted in T1P
if desired. Assertion is now the latest
time possible to allow the CPU to enter
T2P state to maintain pipelining in cycle 3.
READY#
RD#
WR#
LBA#
BS8#
ADS#
In 2
Valid2
Valid3
Valid4
Out 3
Valid1
A25:1, BHE#,
BLE#,UCS#,
CS6:0#, D/C#,
M/IO#
相關PDF資料 |
PDF描述 |
|---|---|
| INTEL386 SXSA | 5-V 32-Bit Fully Static Embedded Microprocessor(5V，32位完全靜態(tài)嵌入式微處理器) |
| intel386 SX | 32-Bit CPU With a 16-Bit External Data Bus And a 24-bit External Address Bus(帶16位內(nèi)部數(shù)據(jù)總線和24位內(nèi)部地址總線32位微處理器) |
| INTEL386 | Intel386 EX Embedded Microprocessor |
| Intel387 dx | DX Math Coprocessor(32位數(shù)學協(xié)處理器) |
| Intel387 sx | SX Math Coprocessor(32位數(shù)學協(xié)處理器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| INTEL386SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:MICROPROCESSOR |
| INTEL387 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM SX MATH COPROCESSOR |
| INTEL387DX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Intel387 DX - MATH COPROCESSOR |
| INTEL387SX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387 SX - MATH COPROCESSOR |
| INTEL387TMDX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel387TM DX MATH COPROCESSOR |
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