參數(shù)資料
型號(hào): Intel386 EX
廠(chǎng)商: Intel Corp.
英文描述: Highly Integrated, 32-Bit, Fully Static Embedded Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器)
中文描述: 高度集成,32位,全靜態(tài)嵌入式Micropocessor(32位高集成完全靜態(tài)嵌入式微處理器)
文件頁(yè)數(shù): 28/48頁(yè)
文件大小: 515K
代理商: INTEL386 EX
Special Environment
Intel386 EX Embedded Processor
24
PRELIMINARY
Interrupt Control Unit (ICU) Outputs
t117
CLK2 High to CAS2:0 Valid
34
DMA Unit Inputs
t118
DREQ Setup Time
(Sync Mode)
17
t119
DREQ Hold Time
(Sync Mode)
4
t120
DREQ Setup Time
(Async Mode)
10
t121
DREQ Hold Time
(Async Mode)
10
t122
EOP# Setup Time
(Sync Mode)
13
t123
EOP# Hold Time
(Sync Mode)
4
t124
EOP# Setup Time
(Async Mode)
10
t125
EOP# Hold Time
(Async Mode)
11
DMA Unit Outputs
t126
DACK# Output Valid Delay
4
29
t127
EOP# Active Delay
4
30
t128
EOP# Float Delay
4
33
(Note 4)
JTAG Test-logic Unit
t129
TCK Frequency
10
(Unit is MHz)
Table 11. AC Characteristics
(Sheet 5 of 5)
Symbol
Parameter
25 MHz
4.75 V to 5.25 V
Test Condition
Min.
(ns)
Max.
(ns)
NOTES:
1. Tested at maximum operating frequency and guaranteed by design characterization at lower operating frequencies.
2. These are not tested. They are guaranteed by characterization.
3. Tested with C
L
set at 50 pF. Timings are guaranteed with C
L
set at 75 pF.
4. Float condition occurs when maximum output current becomes less than I
LO
in magnitude. Float delay is not fully tested.
5. These inputs may be asynchronous to CLK2. The setup and hold specifications are given for testing purposes to ensure
recognition within a specific CLK2 period.
6. These specifications are for information only and are not tested. They are intended to assist the designer in selecting
memory speeds. For each wait state in the design add two CLK2 cycles to the specification.
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