參數(shù)資料
型號(hào)： INTELDX2
廠商： Intel Corp.
英文描述： High-Performance 32-Bit Embedded Processor(高性能32位嵌入式處理器)
中文描述： 高性能32位嵌入式處理器（高性能32位嵌入式處理器）
文件頁(yè)數(shù)： 25/48頁(yè)
文件大小： 486K
代理商： INTELDX2
Embedded IntelDX2 Processor
21
BUS SIZE CONTROL
BS16#
BS8#
I
I
Bus Size 16
and
Bus Size 8
pins (bus sizing pins) cause the embedded IntelDX2
processor to run multiple bus cycles to complete a request from devices that
cannot provide or accept 32 bits of data in a single cycle. The bus sizing pins are
sampled every clock. The processor uses the state of these pins in the clock
before Ready to determine bus size. These signals are active LOW and are
provided with internal pull-up resistors. These inputs must satisfy setup and hold
times t
14
and t
15
for proper operation.
ADDRESS MASK
A20M#
I
Address Bit 20 Mask
pin, when asserted, causes the embedded IntelDX2
processor to mask physical address bit 20 (A20) before performing a lookup to
the internal cache or driving a memory cycle on the bus. A20M# emulates the
address wraparound at 1 Mbyte, which occurs on the 8086 processor. A20M# is
active LOW and should be asserted only when the embedded IntelDX2 processor
is in real mode. This pin is asynchronous but should meet setup and hold times
t
and t
for recognition in any specific clock. For proper operation, A20M#
should be sampled HIGH at the falling edge of RESET.
TEST ACCESS PORT
TCK
I
Test Clock
, an input to the embedded IntelDX2 processor, provides the clocking
function required by the JTAG Boundary scan feature. TCK is used to clock state
information (via TMS) and data (via TDI) into the component on the rising edge of
TCK. Data is clocked out of the component (via TDO) on the falling edge of TCK.
TCK is provided with an internal pull-up resistor.
Test Data Input
is the serial input used to shift JTAG instructions and data into
the processor. TDI is sampled on the rising edge of TCK, during the SHIFT-IR
and SHIFT-DR Test Access Port (TAP) controller states. During all other TAP
controller states, TDI is a “don’t care.” TDI is provided with an internal pull-up
resistor.
Test Data Output
is the serial output used to shift JTAG instructions and data out
of the component. TDO is driven on the falling edge of TCK during the SHIFT-IR
and SHIFT-DR TAP controller states. At all other times TDO is driven to the high
impedance state.
Test Mode Select
is decoded by the JTAG TAP to select test logic operation.
TMS is sampled on the rising edge of TCK. To guarantee deterministic behavior
of the TAP controller, TMS is provided with an internal pull-up resistor.
TDI
I
TDO
O
TMS
I
Table 8.
Embedded IntelDX2 Processor Pin Descriptions
(Sheet 6 of 7)
Symbol
Type
Name and Function
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