參數(shù)資料
型號(hào)： INTELDX2
廠商： Intel Corp.
英文描述： High-Performance 32-Bit Embedded Processor(高性能32位嵌入式處理器)
中文描述： 高性能32位嵌入式處理器（高性能32位嵌入式處理器）
文件頁(yè)數(shù)： 5/48頁(yè)
文件大?。?/td> 486K
代理商： INTELDX2
Embedded IntelDX2 Processor
1
1.0
INTRODUCTION
The embedded IntelDX2 processor provides high
performance to 32-bit, embedded applications.
Designed for applications that need a floating-point
unit, the processor is ideal for embedded designs
running DOS
, Microsoft Windows
, OS/2
, or UNIX
*
applications written for the Intel architecture.
Projects can be completed quickly by utilizing the
wide range of software tools, utilities, assemblers
and compilers that are available for desktop
computer systems. Also, developers can find
advantages in using existing chipsets and peripheral
components in their embedded designs.
The embedded IntelDX2 processor is binary
compatible with the Intel386 and earlier Intel
processors. Compared with the Intel386 processor, it
provides faster execution of many commonly-used
instructions. It also provides the benefits of an
integrated, 8-Kbyte, write-through cache for code
and data. Its data bus can operate in burst mode
which
provides
up
to
transfers
for
cache-line
prefetches.
106-Mbyte-per-second
fills
and
instruction
Intel’s SL technology is incorporated in the
embedded IntelDX2 processor. Utilizing Intel’s
System Management Mode (SMM), it enables
designers to develop energy-efficient systems.
Two component packages are available. A 168-pin
Pin Grid Array (PGA) is available for 5-Volt designs
and a 208-lead Shrink Quad Flat Pack (SQFP) is
available for 3.3-Volt designs.
The processor operates at twice the external-bus
frequency. The 5 V processor operates up to 66
MHz (33-MHz CLK). The 3.3 V processor operates
up to 50 MHz (25-MHz CLK).
1.1
Features
The embedded IntelDX2 processor offers these
features:
32-bit RISC-Technology Core
— The embedded
IntelDX2 processor performs a complete set of
arithmetic and logical operations on 8-, 16-, and
32-bit data types using a full-width ALU and eight
general purpose registers.
Single Cycle Execution
— Many instructions
execute in a single clock cycle.
* Other brands and names are the property of their
respective owners.
Instruction Pipelining
— Overlapped instruction
fetching, decoding, address translation and
execution.
On-Chip Floating-Point Unit
— Intel486
processors support the 32-, 64-, and 80-bit formats
specified in IEEE standard 754. The unit is binary
compatible with the 8087, Intel287, Intel387
coprocessors, and Intel OverDrive
processor.
On-Chip Cache with Cache Consistency
Support
— An 8-Kbyte, write-through, internal
cache is used for both data and instructions.
Cache hits provide zero wait-state access times
for data within the cache. Bus activity is tracked to
detect alterations in the memory represented by
the internal cache. The internal cache can be
invalidated or flushed so that an external cache
controller can maintain cache consistency.
External Cache Control
— Write-back and flush
controls for an external cache are provided so the
processor can maintain cache consistency.
On-Chip Memory Management Unit
— Address
management and memory space protection
mechanisms maintain the integrity of memory in a
multitasking and virtual memory environment. Both
memory segmentation and paging are supported.
Burst Cycles
— Burst transfers allow a new
double-word to be read from memory on each bus
clock cycle. This capability is especially useful for
instruction prefetch and for filling the internal
cache.
Write Buffers
— The processor contains four
write buffers to enhance the performance of
consecutive writes to memory. The processor can
continue internal operations after a write to these
buffers, without waiting for the write to be
completed on the external bus.
Bus Backoff
— When another bus master needs
control of the bus during a processor initiated bus
cycle, the embedded IntelDX2 processor floats its
bus signals, then restarts the cycle when the bus
becomes available again.
Instruction Restart
— Programs can continue
execution following an exception generated by an
unsuccessful attempt to access memory. This
feature is important for supporting demand-paged
virtual memory applications.
Dynamic Bus Sizing
— External controllers can
dynamically alter the effective width of the data
bus. Bus widths of 8, 16, or 32 bits can be used.
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