
Contents
iii
EMBEDDED IntelDX2 PROCESSOR
1.0 INTRODUCTION ........................................................................................................................................1
1.1 Features .............................................................................................................................................1
1.2 Family Members .................................................................................................................................2
2.0 HOW TO USE THIS DOCUMENT .............................................................................................................3
3.0 PIN DESCRIPTIONS .................................................................................................................................3
3.1 Pin Assignments .................................................................................................................................3
3.2 Pin Quick Reference .........................................................................................................................16
4.0 ARCHITECTURAL AND FUNCTIONAL OVERVIEW .............................................................................25
4.1 CPUID Instruction .............................................................................................................................25
4.1.1 Operation of the CPUID Instruction .......................................................................................25
4.2 Identification After Reset ..................................................................................................................26
4.3 Boundary Scan (JTAG) ....................................................................................................................26
4.3.1 Device Identification ...............................................................................................................26
4.3.2 Boundary Scan Register Bits and Bit Order ...........................................................................27
5.0 ELECTRICAL SPECIFICATIONS ...........................................................................................................28
5.1 Maximum Ratings .............................................................................................................................28
5.2 DC Specifications .............................................................................................................................28
5.3 AC Specifications .............................................................................................................................33
5.4 Capacitive Derating Curves ..............................................................................................................39
6.0 MECHANICAL DATA ..............................................................................................................................41
6.1 Package Dimensions ........................................................................................................................41
6.2 Package Thermal Specifications ......................................................................................................44
FIGURES
Figure 1.
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Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Embedded IntelDX2 Processor Block Diagram ...................................................................... i
Package Diagram for 208-Lead SQFP Embedded IntelDX2 Processor ................................4
Package Diagram for 168-Pin PGA Embedded IntelDX2 Processor ...................................10
CLK Waveform ........................................................................................................................35
Input Setup and Hold Timing ...................................................................................................35
Input Setup and Hold Timing ...................................................................................................36
PCHK# Valid Delay Timing ......................................................................................................36
Output Valid Delay Timing .......................................................................................................37
Maximum Float Delay Timing ..................................................................................................37
TCK Waveform ........................................................................................................................38
Test Signal Timing Diagram ....................................................................................................38