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參數(shù)資料
| 型號： | IS43R32400A |
| 廠商： | Integrated Silicon Solution, Inc. |
| 英文描述： | 4Meg x 32 128-MBIT DDR SDRAM |
| 中文描述： | 4Meg × 32的128 - Mbit DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 17/25頁 |
| 文件大?。?/td> | 1295K |
| 代理商： | IS43R32400A |
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00D
02/15/06
17
ISSI
IS43R32400A
COMMANDS
All commands described in this section should be
issued only when the initialization sequence is
obeyed.
Deselect
This feature blocks unwanted commands from being
executed. Chip select (
CS
) must be taken High to
cause Deselect. Operations that are underway are
not affected.
No Operation (NOP)
NOP is a command that prevents new commands from
being executed.
CS
must be Low, while
RAS
,
CAS
,
and
WE
must be High to issue NOP. NOP or Deselect
commands must be issued during wait states to allow
operations that are underway to continue uninter-
rupted.
Load Mode Register
The Base Mode Register is loaded during a step of
initialization to configure the DDR SDRAM. Load
Mode Register (LMR) is issued when BA0 and BA1
are Low, and A0-A11 are selected according to the
Mode Register Definition.
Load Extended Mode Register
The Extended Mode Register is loaded during a step
of initialization to enable the DLL of the device. Load
Extended Mode Register (LMR) is issued when BA0 is
High, BA1 is Low, and A0-A11 are selected according
to the Extended Mode Register Definition.
Read
The Read command is used to begin a burst read
access. When the command is given to the device,
the BA0 and BA1 inputs select the bank, and address
bits A0-A7 (x32) select the block of columns and the
starting column for the subsequent burst. The cross-
ing of the CLK and
CLK
signals will cause the output
values on the I/O pins to be valid. The Auto Pre-
charge function is one option in the Read command. If
the Auto Pre-charge is enabled, the currently selected
row will be pre-charged following the Read burst. If
the function is not enabled, the selected row will
remain open for further accesses at the end of the
Read burst.
Write
The Write command is used to begin a burst write
access. When the command is given to the device,
the BA0 and BA1 inputs select the bank, and address
bits A0-A7 (x32) select the block of columns and the
starting column for the subsequent burst. The rising
edge on the Data Strobe input(s) will cause the input
values on the Data Mask pin(s) and I/O pins to be
sampled for the write operation. The Auto Pre-charge
function is one option in the Write command. If the
Auto Pre-charge is enabled, the currently selected row
will be Pre-charged following the Write burst. If the
function is not enabled, the selected row will remain
open for further accesses at the end of the Write
burst.
Pre-charge
A Pre-charge command will de-activate an open row in
a bank. The input A8 (x32) is sampled at this time to
determine whether Pre-charge is applied to a single
bank or all banks. After tRP, the bank has been pre-
charged. It is de-activated, and goes into the idle
state and must be activated before any Read or Write
command can be issued to it. A Pre-charge command
is treated as a NOP if either (a) the specified bank is
already undergoing Pre-charge, or (b) the specified
bank has no open row.
Auto Pre-charge
Auto Pre-charge is a feature that can be enabled as
an option in a Read or Write command. If the input
value on A8 (x32) is High during a Read or Write
command, an automatic Pre-charge will occur just
after the memory burst is completed. If the input value
on A8 (x32) is Low, no Pre-charge will occur. With
Auto Pre-charge, a minimum time of tRP must pass
before the next command is issued to the same bank.
Active
The Active command opens a row in preparation for a
Read or Write burst. The row stays open for accesses
until the bank receives a Pre-charge command. Other
rows in the bank cannot be opened until the bank is
de-activated with a Pre-charge command and another
Active command is issued.
Burst Terminate
The Burst Terminate command truncates the burst of
the most recently issued Read command (with Auto
Pre-charge disabled). The open row being accessed
in the Read burst remains open.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IS43R32400A-5B | 4Meg x 32 128-MBIT DDR SDRAM |
| IS43R32400A-5BL | 4Meg x 32 128-MBIT DDR SDRAM |
| IS43R32400A-6B | 4Meg x 32 128-MBIT DDR SDRAM |
| IS43R32400A-6BI | 4Meg x 32 128-MBIT DDR SDRAM |
| IS43R32400A-6BL | 4Meg x 32 128-MBIT DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IS43R32400A-5B | 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 4Mx32 400MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R32400A-5BL | 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 4Mx32 400MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R32400A-5BL-TR | 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 4Mx32 400MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R32400A-5B-TR | 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 4Mx32 400MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
| IS43R32400A-6B | 功能描述:動(dòng)態(tài)隨機(jī)存取存儲(chǔ)器 128M 2.5v 4Mx32 333MHz RoHS:否 制造商:ISSI 數(shù)據(jù)總線寬度:16 bit 組織:1 M x 16 封裝 / 箱體:SOJ-42 存儲(chǔ)容量:16 MB 最大時(shí)鐘頻率: 訪問時(shí)間:50 ns 電源電壓-最大:7 V 電源電壓-最小:- 1 V 最大工作電流:90 mA 最大工作溫度:+ 85 C 封裝:Tube |
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