參數(shù)資料
型號: IS64WV20488BLL-10TA3
廠商: INTEGRATED SILICON SOLUTION INC
元件分類: DRAM
英文描述: 2M x 8 HIGH-SPEED CMOS STATIC RAM
中文描述: 2M X 8 STANDARD SRAM, 10 ns, PDSO44
封裝: 0.400 INCH, TSOP2-44
文件頁數(shù): 12/20頁
文件大小: 126K
代理商: IS64WV20488BLL-10TA3
12
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. 00C
01/09/06
ISSI
IS61WV20488ALL
IS61WV20488BLL
IS64WV20488BLL
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
-20 ns
Min.
Symbol
t
WC
t
SCE
t
AW
Parameter
Max.
Unit
Write Cycle Time
20
ns
CE
to Write End
12
ns
Address Setup Time
to Write End
12
ns
t
HA
t
SA
t
PWE
1
t
PWE
2
t
SD
t
HD
t
HZWE
(3)
t
LZWE
(3)
Address Hold from Write End
0
ns
Address Setup Time
0
ns
WE
Pulse Width (
OE
= HIGH)
12
ns
WE
Pulse Width (
OE
= LOW)
17
ns
Data Setup to Write End
9
ns
Data Hold from Write End
0
ns
WE
LOW to High-Z Output
9
ns
WE
HIGH to Low-Z Output
3
ns
Notes:
1. Test conditions assume signal transition times of 1.5ns or less, timing reference levels of 1.25V,
input pulse levels of 0.4V to V
DD
-0.3V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not
100% tested.
3. The internal write time is defined by the overlap of
CE
LOW and
WE
LOW. All signals must be in
valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input
Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the
write.
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