FN6316.1 July 15, 2010 I2C Interface Specifications Test C" />
參數(shù)資料
型號(hào)： ISL1221IUZ-T
廠商： Intersil
文件頁數(shù)： 19/24頁
文件大小： 0K
描述： IC RTC LP BATT BACK SRAM 10MSOP
產(chǎn)品培訓(xùn)模塊： Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)間事件記錄器
特點(diǎn)： 警報(bào)器，閏年，SRAM
存儲(chǔ)容量： 2B
時(shí)間格式： HH:MM:SS（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 2.7 V ~ 5.5 V
電壓 - 電源，電池： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 1245 (CN2011-ZH PDF)
其它名稱： ISL1221IUZ-TDKR
4
FN6316.1
July 15, 2010
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 9)
TYP (Note 5)
MAX
(Note 9)
UNITS NOTES
VIL
SDA and SCL Input Buffer LOW
Voltage
-0.3
0.3 x VDD
V
VIH
SDA and SCL Input Buffer HIGH
Voltage
0.7 x VDD
VDD + 0.3
V
Hysteresis
SDA and SCL Input Buffer
Hysteresis
0.05 x VDD
V
VOL
SDA Output Buffer LOW Voltage,
Sinking 3mA
VDD = 5V, IOL = 3mA
0.4
V
Cpin
SDA and SCL Pin Capacitance
TA = +25°C, f = 1MHz, VDD =5V,
VIN =0V, VOUT =0V
10
pF
fSCL
SCL Frequency
400
kHz
tIN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max
spec is suppressed.
50
ns
tAA
SCL falLing Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of
VDD, until SDA exits the 30% to
70% of VDD window.
900
ns
tBUF
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VDD during
a STOP condition, to SDA
crossing 70% of VDD during the
following START condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VDD
crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VDD
crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling
edge. Both crossing 70% of VDD.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing
30% of VDD to SCL falling edge
crossing 70% of VDD.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to
70% of VDD window, to SCL
rising edge crossing 30% of VDD.
100
ns
tHD:DAT
Input Data Hold Time
From SCL falling edge crossing
30% of VDD to SDA entering the
30% to 70% of VDD window.
0
900
ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing
70% of VDD, to SDA rising edge
crossing 30% of VDD.
600
ns
tHD:STO
STOP Condition Hold Time
From SDA rising edge to SCL
falling edge. Both crossing 70%
of VDD.
600
ns
tDH
Output Data Hold Time
From SCL falling edge crossing
30% of VDD, until SDA enters the
30% to 70% of VDD window.
0ns
tR
SDA and SCL Rise Time
From 30% to 70% of VDD.
20 + 0.1 x Cb
300
ns
tF
SDA and SCL Fall Time
From 70% to 30% of VDD.
20 +
0.1 x Cb
300
ns
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
ISL1221
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