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參數(shù)資料
| 型號： | ISL1221IUZ-T |
| 廠商： | Intersil |
| 文件頁數(shù)： | 3/24頁 |
| 文件大小： | 0K |
| 描述： | IC RTC LP BATT BACK SRAM 10MSOP |
| 產(chǎn)品培訓模塊： | Solutions for Industrial Control Applications |
| 標準包裝： | 1 |
| 類型： | 時間事件記錄器 |
| 特點： | 警報器，閏年，SRAM |
| 存儲容量： | 2B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.8 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 1245 (CN2011-ZH PDF) |
| 其它名稱： | ISL1221IUZ-TDKR |
11
FN6316.1
July 15, 2010
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time base
for the RTC. Since the resonant frequency of a crystal is
temperature dependent, the RTC performance will also be
dependent upon temperature. The frequency deviation of
the crystal is a function of the turnover temperature of the
crystal from the crystal’s nominal frequency. For example, a
~20ppm frequency deviation translates into an accuracy of
~1 minute per month. These parameters are available from
the crystal manufacturer. The ISL1221 provides on-chip
crystal compensation networks to adjust load capacitance to
tune oscillator frequency from -94ppm to +140ppm. For
more detailed information see the “Application Section” on
Single Event and Interrupt
The alarm mode is enabled via the ALME bit. Choosing
single event or interrupt alarm mode is selected via the IM
bit. Note that when the frequency output function is enabled,
the alarm function is disabled.
The standard alarm allows for alarms of time, date, day of
the week, month, and year. When a time alarm occurs in
single event mode, an IRQ/EVDET pin will be pulled low
and the alarm status bit (ALM) will be set to “1”.
The pulsed interrupt mode allows for repetitive or recurring
alarm functionality. Hence, once the alarm is set, the device
will continue to alarm for each occurring match of the alarm
and present time. Thus, it will alarm as often as every minute
(if only the nth second is set) or as infrequently as once a
year (if at least the nth month is set). During pulsed interrupt
mode, the IRQ/EVDET pin will be pulled low for 250ms and
the alarm status bit (ALM) will be set to “1”.
The ALM bit can be reset by the user or cleared
automatically using the auto reset mode (see “Auto Reset
The alarm function can be enabled/disabled during battery
backup mode using the FOBATB bit. For more information
on the alarm, please see the “Alarm Registers” on page 16.
Frequency Output Mode
The ISL1221 has the option to provide a frequency output
signal using the FOUT pin. The frequency output mode is set
by using the FO bits to select 15 possible output frequency
values from 0 to 32kHz. The frequency output can be
enabled/disabled during battery backup mode using the
FOBATB bit.
General Purpose User SRAM
The ISL1221 provides 2 bytes of user SRAM. The SRAM will
continue to operate in battery backup mode. However, it
should be noted that the I2C bus is disabled in battery
backup mode.
I2C Serial Interface
The ISL1221 has an I2C serial bus interface that provides
access to the control and status registers and the user
SRAM. The I2C serial interface is compatible with other
industry I2C serial bus protocols using a bidirectional data
signal (SDA) and a clock signal (SCL).
Oscillator Compensation
The ISL1221 provides the option of timing correction due to
temperature variation of the crystal oscillator for either
manufacturing calibration or active calibration. The total
possible compensation is typically -94ppm to +140ppm. Two
compensation mechanisms that are available are as follows:
1. An analog trimming (ATR) register that can be used to
adjust individual on-chip digital capacitors for oscillator
capacitance trimming. The individual digital capacitor is
selectable from a range of 9pF to 40.5pF (based upon
32.758kHz). This translates to a calculated
compensation of approximately -34ppm to +80ppm. (see
2. A digital trimming register (DTR) that can be used to
adjust the timing counter by ±60ppm. (see “Digital
Also provided is the ability to adjust the crystal capacitance
when the ISL1221 switches from VDD to battery backup
mode. (see “Battery Mode ATR Selection (BMATR <1:0>)”
on page 16 for more details).
Register Descriptions
The battery-backed registers are accessible following a
slave byte of “1101111x” and reads or writes to addresses
[00h:19h]. The defined addresses and default values are
described in the Table 1. Address 09h is not used. Reads or
writes to 09h will not affect operation of the device but should
be avoided.
REGISTER ACCESS
The contents of the registers can be modified by performing
a byte or a page write operation directly to any register
address.
The registers are divided into 5 sections. These are:
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Control and Status (5 bytes): Address 07h to 0Bh.
3. Alarm (6 bytes): Address 0Ch to 11h.
4. User SRAM (2 bytes): Address 12h to 13h.
5. Time Stamp (6 bytes): Address 14h to 19h
There are no addresses above 19h.
Write capability is allowable into the RTC registers (00h to
06h) only when the WRTC bit (bit 4 of address 07h) is set to
“1”. A multi-byte read or write operation is limited to one
section per operation. Access to another section requires a
new operation. A read or write can begin at any address
within the section.
ISL1221
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