FN6316.1 July 15, 2010 X1 pin allows for an external 32kHz signal to drive the RTC. The XTOSCB bit is set to “0” on power up. AUTO RESET ENABLE" />
參數(shù)資料
型號(hào)： ISL1221IUZ-T
廠商： Intersil
文件頁(yè)數(shù)： 6/24頁(yè)
文件大小： 0K
描述： IC RTC LP BATT BACK SRAM 10MSOP
產(chǎn)品培訓(xùn)模塊： Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)間事件記錄器
特點(diǎn)： 警報(bào)器，閏年，SRAM
存儲(chǔ)容量： 2B
時(shí)間格式： HH:MM:SS（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： I²C，2 線串口
電源電壓： 2.7 V ~ 5.5 V
電壓 - 電源，電池： 1.8 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面： 1245 (CN2011-ZH PDF)
其它名稱： ISL1221IUZ-TDKR
14
FN6316.1
July 15, 2010
X1 pin allows for an external 32kHz signal to drive the RTC.
The XTOSCB bit is set to “0” on power up.
AUTO RESET ENABLE BIT (ARST)
This bit enables/disables the automatic reset of the BAT and
ALM, EVT status bits only. When ARST bit is set to “1”, these
status bits are reset to “0” after a valid read of the Status
Register (with a valid STOP condition). When the ARST is
cleared to “0”, the user must manually reset the BAT, ALM,
and EVT bits.
INTERRUPT CONTROL REGISTER (INT)
FREQUENCY OUT CONTROL BITS (FO <3:0>)
These bits enable/disable the frequency output function and
select the output frequency at the FOUT pin. See Table 8 for
frequency selection.
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the FOUT pin during battery backup
mode (i.e. VBAT power source active). When the FOBATB is
set to “1” the FOUT pin is disabled during battery backup
mode. When the FOBATB is cleared to “0”, the FOUT pin is
enabled during battery backup mode. The FOUT pin is open
drain configuration, and when used in battery backup mode
requires a pull up resistor to VBAT.
LOW POWER MODE BIT (LPMODE)
This bit enables/disables low power mode. With
LPMODE = “0”, the device will be in normal mode and the
VBAT supply will be used when VDD < VBAT - VBATHYS and
VDD < VTRIP. With LPMODE = “1”, the device will be in low
power mode and the VBAT supply will be used when
VDD < VBAT -VBATHYS. There is a supply current saving of
about 600nA when using LPMODE = “1” with VDD = 5V.
(See Typical Performance Curves: IDD vs VDD with
LPMODE ON & OFF.)
It should be noted that any writes to the LPMODE bit that
may put the device into Low Power Mode should be avoided
if VDD<VBAT, as the device will no longer communicate over
the I2C interface (until VDD rises above VBAT).
ALARM ENABLE BIT (ALME)
This bit enables/disables the alarm function. When the ALME
bit is set to “1”, the alarm function is enabled. When the ALME
is cleared to “0”, the alarm function is disabled. The alarm
function can operate in either a single event alarm or a periodic
NOTE: When the frequency output mode is enabled, the alarm function
is disabled.
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate
in the interrupt mode, where an active low pulse width of
250ms will appear at the IRQ/EVDET pin when the RTC is
triggered by the alarm as defined by the alarm registers (0Ch
to 11h). When the IM bit is cleared to “0”, the alarm will
operate in standard mode, where the IRQ/EVDET pin will be
tied low until the ALM status bit is cleared to “0”.
EVENT DETECTION REGISTER (EV)
The ISL1221 provides an easy to use event and tamper
detection circuit. The Event Detection Register configures
the functionality of the event detection circuits.
EVENT INPUT SAMPLING SELECTION BITS
(ESMP<1:0>)
These two bits select the rate of sampling of the EVIN pin to
trigger an event detection. For example, a 2Hz sampling rate
would configure the ISL1221 to check the status of the EV
pin twice a second. Slower sampling significantly reduces
the supply current drain.
TABLE 7. INTERRUPT CONTROL REGISTER (INT)
ADDR
7
6
5
4
3210
08h
IM ALME LPMODE FOBATB FO3 FO2 FO1 FO0
Default
0
0000
TABLE 8. FREQUENCY SELECTION OF FOUT PIN
FREQUENCY,
FOUT
UNITS
FO3
FO2
FO1
FO0
0
Hz
0
000
32768
Hz
0
1
4096
Hz
0
1
0
1024
Hz
0
1
64
Hz
0
100
32
Hz
0
101
16
Hz
0
110
8
Hz
0
111
4
Hz
1
000
2
Hz
1
001
1
Hz
1
010
1/2
Hz
1
011
1/4
Hz
1
100
1/8
Hz
1
101
1/16
Hz
1
0
1/32
Hz
1
TABLE 9.
IM BIT
INTERRUPT/ALARM FREQUENCY
0
Single Time Event Set By Alarm
1
Repetitive/Recurring Time Event Set By Alarm
ISL1221
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