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參數(shù)資料
| 型號： | ISL6540A |
| 廠商： | Intersil Corporation |
| 英文描述： | Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability |
| 中文描述： | 單相降壓PWM控制器，帶有集成的高速MOSFET驅(qū)動器和預(yù)偏置負(fù)載能力 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 430K |
| 代理商： | ISL6540A |
14
FN6288.2
March 12, 2007
When MAR_CTRL is left floating, the function is disabled.
Upon UP margining, an internal buffer drives the OFS- pin
from VCC to maintain OFS+ at 0.591V. The resistor divider,
R
MARG
and R
OFS+
, causes the voltage at OFS- to be
increased. Similarly, upon DOWN margining, an internal
buffer drives the OFS+ pin from VCC to maintain OFS- at
0.591V. The resistor divider, R
MARG
and R
OFS-
, causes the
voltage at OFS+ to be increased. In both modes the voltage
difference between OFS+ and OFS- is then sensed with an
instrumentation amplifier and is converted to the desired
margining voltage by a 5:1 ratio. The maximum designed
margining range of the ISL6540A is ±200mV, this sets the
MINIMUM value of R
OFS+
or R
OFS-
at approximately 5.9K
for an R
MARG
of 10K for a MAXIMUM of 1V across R
MARG
.
The OFS pins are completely independent and can be set to
different margining levels. The maximum usable reference
voltage for the ISL6540A is VCC-1.8V, and should not be
exceeded when using the margining functionality, i.e,
V
REF_MARG
< VCC - 1.8V.
An alternative calculation provides for a desired percentage
change in the output voltage when using the internal 0.591V
reference:
When not used in a design OFS+, OFS-, and MARCTRL
should be left floating. To prevent damage to the part, OFS+
and OFS- should not be tied to VCC or PVCC.
Reference Output Buffer
The internal buffer’s output tracks the unmargined system
reference. It has a 19mA drive capability, with maximum and
minimum output voltage capabilities of VCC and GND
respectively. Its capacitive loading can range from 1
μ
F to
above 17.6
μ
F, which is designed for 1 to 8 DIMM systems in
DDR (Dual Data Rate) applications. 1
μ
F of capacitance
should always be present on REFOUT. It is not designed to
drive a resistive load and any such load added to the system
should be kept above 300k
Ω
total impedance. The
Reference Output Buffer should not be left floating.
Reference Input
The REFIN pin allows the user to bypass the internal 0.591V
reference with an external reference. Asynchronously if
REFIN is NOT within ~1.8V of VCC, the external reference
pin is used as the control reference instead of the internal
0.591V reference. The minimum usable REFIN voltage is
~68mV while the maximum is VCC - 1.8V - V
MARG
(if
present).
Internal Reference and System Accuracy
The internal reference is trimmed to 0.591V. The total DC
system accuracy of the system is within ±0.68% over
commercial temperature range, and ±1.00% over industrial
temperature range. System accuracy includes error amplifier
offset, OTA error, and bandgap error. Differential remote
sense offset error is not included. As a result, if the
differential remote sense is used, then an extra 1.9mV of
offset error enters the system. The use of REFIN may add
up to 2.2mV of additional offset error.
Differential Remote Sense Buffer
The differential remote sense buffer is essentially an
instrumentation amplifier with unity gain. The offset is
trimmed to 1.5mV for high system accuracy. As with any
instrumentation amplifier typically 6
μ
A are sourced from the
VSEN- pin. The output of the remote sense buffer is
connected directly to the internal OV/UV comparator. As a
result, a resistor divider should be placed on the input of the
buffer for proper regulation, as shown in Figure 6. The
VMON pin should be connected to the FB pin by a standard
feed-back network. A small capacitor, C
SEN
in Figure 6, can
be added to filter out noise, typically C
SEN
is chosen so the
corresponding time constant does not reduce the overall
phase margin of the design, typically this is 2x to 10x
switching frequency of the regulator.
As some applications will not use the differential remote
sense, the output of the remote sense buffer can be disabled
(high impedance) by pulling VSEN- within 1.8V of VCC. As
the VMON pin is connected internally to the OV/UV/PGOOD
comparator, an external resistor divider must then be
connected to VMON to provide correct voltage information
for the OV/UV comparator. An RC filter should be used if
VMON is to be connected directly to FB instead of to VOUT
through a separate resistor divider network. This filter
prevents noise injection from disturbing the OV/UV/PGOOD
comparators on VMON. VMON may also be connected to
the SS pin, which completely bypasses the OV/UV/PGOOD
functionality.
V
MARG_DOWN
V
--------------
R
OFS-
--------------------
=
V
MARG_UP
V
--------------
R
OFS+
--------------------
=
V
pct_DOWN
20
R
OFS-
--------------------
=
V
PCT_UP
20
R
OFS+
--------------------
=
FIGURE 5. SIMPLIFIED REFERENCE BUFFER
OTA
800mV
V
REF_MARG
ISL6540A
STATE
MACHINE
REFERENCE
V
REF
=0.591V
REFIN
REFOUT
VCC
MARGINING
BLOCK
ISL6540A
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