參數(shù)資料
型號(hào)： ISL6540A
廠商： Intersil Corporation
英文描述： Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability
中文描述： 單相降壓PWM控制器，帶有集成的高速M(fèi)OSFET驅(qū)動(dòng)器和預(yù)偏置負(fù)載能力
文件頁(yè)數(shù)： 17/20頁(yè)
文件大?。?/td> 430K
代理商： ISL6540A
17
FN6288.2
March 12, 2007
to 0.16 multiplied by the voltage at the VFF pin. When
tieing VFF to V
IN
the above equation simplifies to:
0.16 R
F
0
LC
2. Calculate C
1
such that F
Z1
is placed at a fraction of the F
LC
,
at 0.1 to 0.75 of F
LC
(to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F
CE
/F
LC
, the lower the F
Z1
frequency (to maximize phase boost at F
LC
).
2
LC
3. Calculate C
2
such that F
P1
is placed at F
CE
.
C
2
1
CE
4. Calculate R
3
such that F
Z2
is placed at F
LC
. Calculate C
3
such that F
P2
is placed below F
SW
(typically, 0.5 to 1.0
times F
SW
). F
SW
represents the regulator’s switching
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F
P2
lower in frequency
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizing resultant duty cycle jitter.
R
LC
3
SW
It is recommended that a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
MOD
), feedback
compensation (G
FB
) and closed-loop response (G
CL
):
As before when tieing VFF to VIN terms in the above
equations can be simplified as follows:
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 11 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual modulator gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F
P2
against the capabilities of the error
amplifier. The closed loop gain, G
CL
, is constructed on the
log-log graph of Figure 11 by adding the modulator gain,
G
MOD
(in dB), to the feedback compensation gain, G
FB
(in
dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the switching frequency, F
SW
.
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
R
2
----------------------------------
=
C
1
----------------------------------------------
=
C
2
1
–
-------------------------------------------------------
=
R
3
------------
1
–
---------------------
=
C
3
------------------------------------------------
=
G
MOD
f
( )
D
V
OSC
------------------------------
1
s f
( )
ESR
DCR
+
(
)
C
s
2
f
( )
L C
+
+
----------------------------------+
=
G
FB
f
( )
1
s f
( )
R
C
1
+
1
C
2
)
--------------------------------------+
=
1
s f
( )
R
R
+
(
)
C
+
1
s f
( )
R
3
C
3
+
(
)
1
s f
( )
R
2
2
1
C
2
+
--------------------
+
-------------------------------------------------------------------------------------------------------------------------
G
CL
f
( )
G
MOD
f
( )
G
FB
f
( )
=
where s f
( )
,
2
π
=
D
V
OSC
------------------------------
1 V
IN
--------------------------
6.25
=
=
F
Z1
2
1
------------------------------
=
F
Z2
1
R
3
)
C
3
-----------------------+
=
F
P1
2
π
R
2
2
1
C
2
+
--------------------
--------------------------------------------
=
F
P2
3
3
------------------------------
=
0
F
P1
F
Z2
OPEN LOOP E/A GAIN
F
Z1
F
P2
F
LC
F
CE
COMPENSATION GAIN
CLOSED LOOP GAIN
G
FREQUENCY
MODULATOR GAIN
FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
20
D
OSC
V
IN
-----V
log
20
R1
log
LOG
L
F
0
G
MOD
G
FB
G
CL
ISL6540A
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