30 FN7717.2 November 30, 2012 SPI Memory Map ADDR. (Hex) PARAMETER NAME BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) DE" />
參數(shù)資料
型號(hào)： ISLA212P20IRZ
廠商： Intersil
文件頁數(shù)： 24/36頁
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL/SPI 72QFN
標(biāo)準(zhǔn)包裝： 1
系列： FemtoCharge™
位數(shù)： 12
采樣率（每秒）： 200M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 468mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤
輸入數(shù)目和類型： *
ISLA212P
30
FN7717.2
November 30, 2012
SPI Memory Map
ADDR.
(Hex)
PARAMETER NAME
BIT 7 (MSB)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0 (LSB)
DEF. VALUE
(HEX)
SPI
Config
/Contr
ol
00
Port_config
SDO Active
LSB First
Soft Reset
Mirror (bit5) Mirror (bit6) Mirror (bit7)
00h
01
Reserved
02
Burst_end
Burst end address [7:0]
00h
03-07
Reserved
DUT
Info
08
Chip_id
Chip ID #
Read only
09
Chip_version
Chip Version #
Read only
0A-0F
Reserved
D
ev
ic
eC
on
fig
/C
on
tr
ol
10-1F
Reserved
20
Offset_coarse_adc0
Coarse Offset
cal. value
21
Offset_fine_adc0
Fine Offset
cal. value
22
Gain_coarse_adc0
Reserved
Coarse Gain
cal. value
23
Gain_medium_adc0
Medium Gain
cal. value
24
Gain_fine_adc0
Fine Gain
cal. value
25
Modes_adc0
Reserved
Power Down Mode ADC0 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
00h
NOT reset by
Soft Reset
26
Offset_coarse_adc1
Coarse Offset
cal. value
27
Offset_fine_adc1
Fine Offset
cal. value
28
Gain_coarse_adc1
Reserved
Coarse Gain
cal. value
29
Gain_medium_adc1
Medium Gain
cal. value
2A
Gain_fine_adc1
Fine Gain
cal. value
2B
Modes_adc1
Reserved
Power Down Mode ADC1 [2:0]
000 = Pin Control
001 = Normal Operation
010 = Nap
100 = Sleep
Other codes = Reserved
00h
NOT reset by
Soft Reset
2C-2F
Reserved
30-4A
Reserved
4B
Temp_counter_high
Temp Counter [10:8]
Read only
4C
Temp_counter_low
Temp Counter [7:0]
Read only
4D
Temp_counter_control
Enable
PD
Reset
Divider [2:0]
Select
00h
4E-6F
Reserved
70
Skew_diff
Differential Skew
80h
71
Phase_slip
Reserved
Next Clock
Edge
00h
72
Clock_divide
Clock Divide [2:0]
000 = Pin Control
001 = divide by 1
010 = divide by 2
100 = divide by 4
Other codes = Reserved
00h
NOT reset by
Soft Reset
73
Output_mode_A
Output Mode [7:5]
000 = LVDS 3mA (Default)
001 = LVDS 2mA
100 = LVCMOS
Other codes = Reserved
Output Format [2:0]
000 = Two’s Complement (Default)
010 = Gray Code
100 = Offset Binary
Other codes = Reserved
00h
NOT reset by
Soft Reset
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