33 FN7717.2 November 30, 2012 A/D Evaluation Platform Intersil offers an A/D Evaluation platform that can be used to evaluate any of t" />
參數(shù)資料
型號(hào)： ISLA212P20IRZ
廠商： Intersil
文件頁(yè)數(shù)： 27/36頁(yè)
文件大小： 0K
描述： IC ADC 12BIT SRL/SPI 72QFN
標(biāo)準(zhǔn)包裝： 1
系列： FemtoCharge™
位數(shù)： 12
采樣率（每秒）： 200M
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 468mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 72-QFN（10x10）
包裝： 托盤
輸入數(shù)目和類型： *
ISLA212P
33
FN7717.2
November 30, 2012
A/D Evaluation Platform
Intersil offers an A/D Evaluation platform that can be used to
evaluate any of the Intersil high-speed A/D products. The
platform consists of an FPGA-based data capture motherboard
and a family of A/D daughtercards. This USB-based platform
allows a user to quickly evaluate the A/D performance at
user-specific application frequency requirements. More
information is available at
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies require
extra care in PC board layout. Many complex board designs
benefit from isolating the analog and digital sections. Analog
supply and ground planes should be laid out under signal and
clock inputs. Locate the digital planes under outputs and logic
pins. Grounds should be joined under the chip.
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the
analog input and clock signals. Locate transformers and
terminations as close to the chip as possible.
Exposed Paddle
The exposed paddle must be electrically connected to analog
ground (AVSS) and for optimal thermal performance should be
connected to a large copper plane using numerous vias.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance.
Tantalum is a good choice. For best performance, keep ceramic
bypass capacitors very close to device pins. Longer traces
increase inductance, resulting in diminished dynamic
performance and accuracy. Make sure that connections to
ground are direct and low impedance. Avoid forming ground
loops.
LVDS Outputs
Output traces and connections must be designed for 50
Ω (100Ω
differential) characteristic impedance. Keep traces direct, and
minimize bends where possible. Avoid crossing ground and
power-plane breaks with signal traces.
LVCMOS Outputs
Output traces and connections must be designed for 50
Ω
characteristic impedance.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) that are
not operated do not require connection to ensure optimal A/D
performance. These inputs can be left floating if they are not
used. Tri-level inputs (NAPSLP) accept a floating input as a valid
state and therefore should be biased according to the desired
functionality.
Definitions
Analog Input Bandwidth is the analog input frequency at which
the spectral output power at the fundamental frequency (as
determined by FFT analysis) is reduced by 3dB from its full-scale
low-frequency value. This is also referred to as Full Power
Bandwidth.
Aperture Delay or Sampling Delay is the time required after the
rise of the clock input for the sampling switch to open, at which
time the signal is held for conversion.
Aperture Jitter is the RMS variation in aperture delay for a set of
samples.
Clock Duty Cycle is the ratio of the time the clock wave is at logic
high to the total time of one clock period.
Differential Non-Linearity (DNL) is the deviation of any code width
from an ideal 1 LSB step.
Effective Number of Bits (ENOB) is an alternate method of
specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it
is calculated as: ENOB = (SINAD - 1.76)/6.02
Gain Error is the ratio of the difference between the voltages that
cause the lowest and highest code transitions to the full-scale
voltage less than 2 LSB. It is typically expressed in percent.
FIGURE 49. VCM_OUT OUTPUT
Equivalent Circuits (Continued)
VCM
AVDD
0.94V
+
–
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