13 FN7717.2 November 30, 2012 FIGURE 2B. CMOS SDR FIGURE 2. CMOS TIMING DIAGRAMS Timing Diagrams
參數(shù)資料
型號: ISLA212P20IRZ
廠商: Intersil
文件頁數(shù): 5/36頁
文件大小: 0K
描述: IC ADC 12BIT SRL/SPI 72QFN
標(biāo)準(zhǔn)包裝: 1
系列: FemtoCharge™
位數(shù): 12
采樣率(每秒): 200M
數(shù)據(jù)接口: 串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 468mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 72-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 72-QFN(10x10)
包裝: 托盤
輸入數(shù)目和類型: *
ISLA212P
13
FN7717.2
November 30, 2012
FIGURE 2B. CMOS SDR
FIGURE 2. CMOS TIMING DIAGRAMS
Timing Diagrams (Continued)
CLKN
CLKP
INP
INN
tA
CLKOUT
tCPD
D[11:0]
LATENCY = L CYCLES
tDC
tPD
DATA
N-L
DATA
N-L+1
DATA
N
Switching Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
CONDITION
MIN
(Note 5)
TYP
MAX
(Note 5)
UNITS
ADC OUTPUT
Aperture Delay
tA
114
ps
RMS Aperture Jitter
jA
75
fs
Input Clock to Output Clock Propagation
Delay
tCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
1.65
2.4
3
ns
tCPD
AVDD, OVDD = 1.8V, TA = +25°C
1.9
2.3
2.75
ns
Relative Input Clock to Output Clock
Propagation Delay (Note 12)
dtCPD
AVDD, OVDD = 1.7V to 1.9V,
TA = -40°C to +85°C
-450
450
ps
Input Clock to Data Propagation Delay
tPD
1.65
2.4
3.5
ns
Output Clock to Data Propagation Delay,
LVDS Mode
tDC
Rising/Falling Edge
-0.1
0.16
0.5
ns
Output Clock to Data Propagation Delay,
CMOS Mode
tDC
Rising/Falling Edge
-0.1
0.2
0.65
ns
Synchronous Clock Divider Reset Setup
Time (with respect to the positive edge of
CLKP)
tRSTS
0.4
0.06
ns
Synchronous Clock Divider Reset Hold Time
(with respect to the positive edge of CLKP)
tRSTH
0.02
0.35
ns
Synchronous Clock Divider Reset Recovery
Time
tRSTRT
DLL recovery time after
Synchronous Reset
52
s
Latency (Pipeline Delay)
L
10
cycles
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